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SAM4CP [DATASHEET]
43051E–ATPL–08/14
21.
General-Purpose Backup Registers (GPBR)
21.1
Description
The System Controller embeds 16 General-purpose Backup registers.
It is possible to generate an immediate clear of the content of General-purpose Backup registers 0 to 7
(first half), if
a Tamper event is detected on one of the tamper pins, TMP0 to TMP3. The content of the other General-purpose Backup
registers (second half) remains unchanged. The Tamper events on pins TMP1 to TMP3 to perform a GPBR clear are
configurable in the Supply Controller. The TMP0 Tamper event always performs an immediate clear.
The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply Controller
module, LPDBCCLR, LPDBCEN0, LPDBCEN1, LPDBCEN2 and and LPDBCEN3 bit must be configured to 1 and
LPDBC must be other than 0.
If a Tamper event has been detected, it is not possible to write to the General-purpose Backup registers while the
LPDBCSx flags are not cleared in the Supply Controller Status register SUPC_SR.
21.2
Embedded Characteristics
16 32-bit General Purpose Backup Registers
21.3
General Purpose Backup Registers (GPBR) User Interface
Table 21-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x0
General Purpose Backup Register 0
SYS_GPBR0
Read/Write
0x00000000
...
...
...
...
...
0xCC
General Purpose Backup Register 15
SYS_GPBR15
Read/Write
0x00000000