參數(shù)資料
型號: PT7A4410
英文描述: PWM Waveform Generator Accelerator Verilog Module
中文描述: T1/E1/OC3系統(tǒng)同步?
文件頁數(shù): 26/34頁
文件大小: 306K
代理商: PT7A4410
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
PT0100(08/02)
Ver:0
32
Test Conditions:
1. PRI reference input selected.
2. SEC reference input selected.
3. Normal State selected.
4. Holdover State selected.
5. Free-Run State selected.
6. 8kHz frequency source selected.
7. 1.544MHz frequency source selected.
8. 2.048MHz frequency source selected.
9. Master clock input OSCi at 20MHz ±0ppm.
10. Master clock input OSCi at 20MHz ±32ppm.
11. Master clock input OSCi at 20MHz ±100ppm.
12. Selected reference input at ±0ppm.
13. Selected reference input at ±32ppm.
14. Selected reference input at ±100ppm.
15. For Free-Run State of ±0ppm.
16. For Free-Run State of ±32ppm.
17. For Free-Run State of ±100ppm.
18. For capture range of ±230ppm.
19. For capture range of ±198ppm.
20. For capture range of ±130ppm.
21. 25pF capacitive load.
22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI
p-p where 1UI p-p = 1/20MHz.
23. Jitter on reference input is less than 7ns p-p.
24. Applied jitter is sinusoidal.
25. Minimum applied input jitter magnitude to regain syn-
chronization.
26. Loss of synchronization is obtained at slightly higher in-
put jitter amplitudes.
27. Within 10ms of the state, reference or input change.
28. 1UIpp = 125
s for 8kHz signals.
29. 1UIpp = 648ns for 1.544MHz signals.
30. 1UIpp = 488ns for 2.048MHz signals.
31. 1UIpp = 324ns for 3.088MHz signals.
32. 1UIpp = 244ns for 4.096MHz signals.
33. 1UIpp = 122ns for 8.192MHz signals.
34. 1UIpp = 61ns for 16.384MHz signals.
35. No filter.
36. 40Hz to 100kHz bandpass filter.
37. With respect to reference input signal frequency.
38. After a RST or TCLR.
39. Master clock duty cycle 40% to 60%.
40. Prior to Holdover State, device was in Normal State and
phase locked.
Notes:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Supply voltage and operation temperature are as per Recommended Operating Conditions.
3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.
相關(guān)PDF資料
PDF描述
PT7A4410L Incremental Encoder Interface Accelerator Verilog Module
PT7A5020 Power Diagnostics Function Accelerator Verilog Module
PT7A6525 Reference design kit featuring a High Power Class D Audio Power Amplifier
PT7A6525L 60V Single N-Channel HEXFET Power MOSFET in a TO-247AC package
PT7A6526 50V Fast Recovery Diode in a DO-203AB (DO-5) package
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PT7A4410J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer
PT7A4410L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer
PT7A4410LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer
PT7A5020 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2048 Ports Non-Blocking Time-Slot Switch?
PT7A6525 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual-channel Protocol Controller? | User's manual for PT7A6525(6) demo system in DMA mode?(PDF)