VDD should not be allowed to " />
參數(shù)資料
型號(hào)： DSP56F826BU80E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 17/56頁(yè)
文件大?。?/td> 0K
描述： IC DSP 80MHZ 64KB FLASH 100LQFP
標(biāo)準(zhǔn)包裝： 90
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 46
程序存儲(chǔ)器容量： 67KB（33.5K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4.5K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 2.75 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤(pán)
56F826 Technical Data, Rev. 14
24
Freescale Semiconductor
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (2.5V) from the voltage generated by the 3.3V VDDIO supply, see Figure 3-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 3-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 1.4, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 1.4V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
Figure 3-3 Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested using the VIL and VIHlevels specified in the DC Characteristics
table. The levels of VIH and VIL for an input signal are shown in Figure 3-4.
Figure 3-4 Input Signal Measurement References
Figure 3-5 shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
3.3V
Regulator
2.5V
Regulator
Supply
VDD
VDDIO, VDDA
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low
High
Pulse Width
90%
50%
10%
Rise Time
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參數(shù)描述
DSP56F826BU80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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DSP56F826E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F826EVM 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F826 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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