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參數(shù)資料
| 型號： | DSP56F805FV80E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 38/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | 56F8xx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 71KB（35.5K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.5K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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Controller Area Network (CAN) Timing
56F805 Technical Data, Rev. 16
Freescale Semiconductor
43
1.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4.
Sampling capacitor at the sample and hold circuit. (1pf)
Figure 3-27 Equivalent Analog Input Circuit
3.13 Controller Area Network (CAN) Timing
ADC Quiescent Current (both ADCs)
IADC
—50
—
mA
VREF Quiescent Current (both ADCs)
IVREF
—12
16.5
mA
1.
For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital
output code of 0.
2.
VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VD-
DA-0.3V.
3.
.Measured in 10-90% range.
4.
LSB = Least Significant Bit.
5.
Guaranteed by characterization.
6.
tAIC = 1/fADIC
Table 3-17 CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, MSCAN Clock = 30MHz
Characteristic
Symbol
Min
Max
Unit
Baud Rate
BRCAN
—1
Mbps
Bus Wakeup detection 1
1.
If Wakeup glitch filter is enabled during the design initialization and also CAN is put into Sleep mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection
takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact
that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
2.
Parameters listed are guaranteed by design.
T WAKEUP
5—
us
Table 3-16 ADC Characteristics (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
1
2
3
4
ADC analog input
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