參數(shù)資料
型號(hào): DSP56F805FV80E
廠商: Freescale Semiconductor
文件頁數(shù): 25/56頁
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝: 60
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 71KB(35.5K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
External Clock Operation
56F805 Technical Data, Rev. 16
Freescale Semiconductor
31
3.5.4
Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
fosc
48
10
MHz
PLL output frequency2
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
fout/2
40
110
MHz
PLL stabilization time 3 0o to +85oC
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
tplls
—1
10
ms
PLL stabilization time3 -40o to 0oC
tplls
100
200
ms
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