Operating Conditions:
參數(shù)資料
型號: DSP56F805FV80E
廠商: Freescale Semiconductor
文件頁數(shù): 19/56頁
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝: 60
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 71KB(35.5K x 16)
程序存儲器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
56F805 Technical Data, Rev. 16
26
Freescale Semiconductor
Table 3-7 Flash Timing Parameters
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL 50pF
Characteristic
Symbol
Min
Typ
Max
Unit
Figure
Program time
Tprog*
20
us
Erase time
Terase*
20
ms
Mass erase time
Tme*
100
ms
Endurance1
1.
One cycle is equal to an erase program and read.
ECYC
10,000
20,000
cycles
Data Retention1
DRET
10
30
years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set up
time
Tnvs*
–5
us
NVSTR hold time
Tnvh*
–5
us
NVSTR hold time (mass erase)
Tnvh1*
100
us
NVSTR to program set up time
Tpgs*
–10
us
Recovery time
Trcv*
–1
us
Cumulative program
HV period2
2.
Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be pro-
grammed twice before next erase.
Thv
–3
ms
Program hold time3
3.
Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
Tpgh
––
Address/data set up time3
Tads
––
Address/data hold time3
Tadh
––
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