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參數(shù)資料
| 型號(hào)： | DSP56F805FV80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/56頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | 56F8xx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 71KB（35.5K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2.5K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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56F805 Technical Data, Rev. 16
4
Freescale Semiconductor
Part 1 Overview
1.1 56F805 Features
1.1.1
Processing Core
Efficient 16-bit 56800 family processor engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
× 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators, including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
—31.5K
× 16 bit words of Program Flash
—512
× 16-bit words of Program RAM
—4K
× 16-bit words of Data Flash
—2K
× 16-bit words of Data RAM
—2K
× 16-bit words of Boot Flash
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
× 16 bits of Data memory
— As much as 64K
× 16 bits of Program memory
1.1.3
Peripheral Circuits for 56F805
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four
Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-aligned modes
Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and
PWM modules can be synchronized
Two Quadrature Decoders each with four inputs or two additional Quad Timers
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F805FV80E | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP144 3.6V |
| DSP56F805PB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F805 16-Bit Hybrid Controller Product Brief |
| DSP56F807 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F807 16-bit Hybrid Processor |
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