參數(shù)資料
型號(hào): DSP56F805FV80
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 31/56頁(yè)
文件大?。?/td> 0K
描述: IC DSP 80MHZ 64KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝: 60
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 71KB(35.5K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤(pán)
Serial Peripheral Interface (SPI) Timing
56F805 Technical Data, Rev. 16
Freescale Semiconductor
37
3.8 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50pF, fOP = 80MHz
1.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
50
25
ns
Figures
Enable lead time
Master
Slave
tELD
25
ns
Figure 3-22
Enable lag time
Master
Slave
tELG
100
ns
Figure 3-22
Clock (SCLK) high time
Master
Slave
tCH
17.6
12.5
ns
Figures
Clock (SCLK) low time
Master
Slave
tCL
24.1
25
ns
Figure 3-22
Data set-up time required for inputs
Master
Slave
tDS
20
0
ns
Figures
Data hold time required for inputs
Master
Slave
tDH
0
2
ns
Figures
Access time (time to data active from
high-impedance state)
Slave
tA
4.8
15
ns
Figure 3-22
Disable time (hold time to high-impedance state)
Slave
tD
3.7
15.2
ns
Figure 3-22
Data Valid for outputs
Master
Slave (after enable edge)
tDV
4.5
20.4
ns
Figures
Data invalid
Master
Slave
tDI
0
ns
Figures
Rise time
Master
Slave
tR
11.5
10.0
ns
Figures
Fall time
Master
Slave
tF
9.7
9.0
ns
Figures
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