參數(shù)資料
型號: DSP56F803BU80
廠商: Freescale Semiconductor
文件頁數(shù): 45/52頁
文件大?。?/td> 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
標準包裝: 90
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 71KB(35.5K x 16)
程序存儲器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
56F803 Description
56F803 Technical Data, Rev. 16
Freescale Semiconductor
5
Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external
pins and Timer D with two pins
CAN 2.0 B module with 2-pin ports for transmit and receive
Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
Computer Operating Properly (COP) Watchdog timer
Two dedicated external interrupt pins
Sixteen multiplexed General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
JTAG/On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F803 Description
The 56F803 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact device and control code.
The instruction set is also highly efficient for C compilers to enable rapid development of optimized
control applications.
The 56F803 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external
dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory.
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
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