參數(shù)資料
型號： DSP56364P
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號處理器
文件頁數(shù)： 50/148頁
文件大?。?/td> 1204K
代理商： DSP56364P
External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4
3-34
Freescale Semiconductor
173
Column address valid to CAS assertion
t
ASC
0.75
×
T
C
4.0
3.5
—
ns
174
CAS assertion to column address not valid
t
CAH
6.25
×
T
C
4.0
58.5
—
ns
175
RAS assertion to column address not valid
t
AR
9.75
×
T
C
4.0
93.5
—
ns
176
Column address valid to RAS deassertion
t
RAL
7
×
T
C
4.0
66.0
—
ns
177
WR deassertion to CAS assertion
t
RCS
5
×
T
C
3.8
46.2
—
ns
178
CAS deassertion to WR
4
assertion
t
RCH
1.75
×
T
C
3.7
13.8
—
ns
179
RAS deassertion to WR
4
assertion
t
RRH
0.25
×
T
C
2.0
0.5
—
ns
180
CAS assertion to WR deassertion
t
WCH
6
×
T
C
4.2
55.8
—
ns
181
RAS assertion to WR deassertion
t
WCR
9.5
×
T
C
4.2
90.8
—
ns
182
WR assertion pulse width
t
WP
15.5
×
T
C
4.5
150.5
—
ns
183
WR assertion to RAS deassertion
t
RWL
15.75
×
T
C
4.3
153.2
—
ns
184
WR assertion to CAS deassertion
t
CWL
14.25
×
T
C
4.3
138.2
—
ns
185
Data valid to CAS assertion (write)
t
DS
8.75
×
T
C
4.0
83.5
—
ns
186
CAS assertion to data not valid (write)
t
DH
6.25
×
T
C
4.0
58.5
—
ns
187
RAS assertion to data not valid (write)
t
DHR
9.75
×
T
C
4.0
93.5
—
ns
188
WR assertion to CAS assertion
t
WCS
9.5
×
T
C
4.3
90.7
—
ns
189
CAS assertion to RAS assertion (refresh)
t
CSR
1.5
×
T
C
4.0
11.0
—
ns
190
RAS deassertion to CAS assertion (refresh)
t
RPC
4.75
×
T
C
4.0
43.5
—
ns
191
RD assertion to RAS deassertion
t
ROH
15.5
×
T
C
4.0
151.0
—
ns
192
RD assertion to data valid
t
GA
14
×
T
C
5.7
—
134.3
ns
193
RD deassertion to data not valid
3
t
GZ
0.0
—
ns
194
WR assertion to data active
0.75
×
T
C
0.3
7.2
—
ns
195
WR deassertion to data high impedance
0.25
×
T
C
—
2.5
ns
1
The number of wait states for out-of-page access is specified in the DCR.
2
The refresh period is specified in the DCR.
3
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ
.
4
Either t
RCH
or t
RRH
must be satisfied for read cycles.
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
1, 2
(continued)
No.
Characteristics
3
Symbol
Expression
Min
Max
Unit
相關PDF資料
PDF描述
DSP56366P 24-Bit Audio Digital Signal Processor
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
相關代理商/技術參數(shù)
參數(shù)描述
DSP56364UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual
DSP56366 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor
DSP56366P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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