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| 型號： | DSP56311VL150B1 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 67/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 384kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Power
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-3
1.1 Power
1.2 Ground
1.3 Clock
Table 1-2.
Power Inputs
Power Name
Description
VCCP
PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the VCC power rail.
VCCQL
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from
all other chip power inputs.
VCCQH
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip
power inputs
, except VCCQL.
VCCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
to all other chip power inputs,
except VCCQL.
VCCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
other chip power inputs,
except VCCQL.
VCCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
chip power inputs,
except VCCQL.
VCCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs,
except VCCQL.
VCCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs,
except VCCQL.
Note: The user must provide adequate external decoupling capacitors for all power connections.
Table 1-3.
Grounds
Name
Description
GNDP
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip
package.
GNDP1
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
GND
Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
Table 1-4.
Clock Signals
Signal Name
Type
State During
Reset
Signal Description
EXTAL
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
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