DRAM Out-of-Page and Refresh " />
參數(shù)資料
型號(hào)： DSP56303VL100B1
廠商： Freescale Semiconductor
文件頁數(shù)： 45/108頁
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-BGA
標(biāo)準(zhǔn)包裝： 630
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-21
Table 2-12.
DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1,2
No.
Characteristics
Symbol
Expression3
100 MHz
Unit
Min
Max
157
Random read or write cycle time
tRC
16
× T
C
160.0
—
ns
158
RAS assertion to data valid (read)
tRAC
8.25
× TC 5.7
—
76.8
ns
159
CAS assertion to data valid (read)
tCAC
4.75
× TC 5.7
—
41.8
ns
160
Column address valid to data valid (read)
tAA
5.5
× T
C 5.7
—
49.3
ns
161
CAS deassertion to data not valid (read hold time)
tOFF
0.0
—
ns
162
RAS deassertion to RAS assertion
tRP
6.25
× TC 4.0
58.5
—
ns
163
RAS assertion pulse width
tRAS
9.75
× T
C 4.0
93.5
—
ns
164
CAS assertion to RAS deassertion
tRSH
6.25
× TC 4.0
58.5
—
ns
165
RAS assertion to CAS deassertion
tCSH
8.25
× TC 4.0
78.5
—
ns
166
CAS assertion pulse width
tCAS
4.75
× T
C 4.0
43.5
—
ns
167
RAS assertion to CAS assertion
tRCD
3.5
× TC ± 233.0
37.0
ns
168
RAS assertion to column address valid
tRAD
2.75
× TC ± 225.5
29.5
ns
169
CAS deassertion to RAS assertion
tCRP
7.75
× T
C 4.0
73.5
—
ns
170
CAS deassertion pulse width
tCP
6.25
× TC – 6.0
56.5
—
ns
171
Row address valid to RAS assertion
tASR
6.25
× TC 4.0
58.5
—
ns
172
RAS assertion to row address not valid
tRAH
2.75
× T
C 4.0
23.5
—
ns
173
Column address valid to CAS assertion
tASC
0.75
× TC 4.0
3.5
—
ns
174
CAS assertion to column address not valid
tCAH
6.25
× TC 4.0
58.5
—
ns
175
RAS assertion to column address not valid
tAR
9.75
× T
C 4.0
93.5
—
ns
176
Column address valid to RAS deassertion
tRAL
7
× TC 4.0
66.0
—
ns
177
WR deassertion to CAS assertion
tRCS
5
× TC 3.8
46.2
—
ns
178
CAS deassertion to WR4 assertion
tRCH
1.75
× T
C – 3.7
13.8
—
ns
179
RAS deassertion to WR
4 assertion
tRRH
0.25
× TC 2.0
0.5
—
ns
180
CAS assertion to WR deassertion
tWCH
6
× TC 4.2
55.8
—
ns
181
RAS assertion to WR deassertion
tWCR
9.5
× T
C 4.2
90.8
—
ns
182
WR assertion pulse width
tWP
15.5
× TC 4.5
150.5
—
ns
183
WR assertion to RAS deassertion
tRWL
15.75
× TC 4.3
153.2
—
ns
184
WR assertion to CAS deassertion
tCWL
14.25
× T
C 4.3
138.2
—
ns
185
Data valid to CAS assertion (write)
tDS
8.75
× TC 4.0
83.5
—
ns
186
CAS assertion to data not valid (write)
tDH
6.25
× TC 4.0
58.5
—
ns
187
RAS assertion to data not valid (write)
tDHR
9.75
× T
C 4.0
93.5
—
ns
188
WR assertion to CAS assertion
tWCS
9.5
× TC 4.3
90.7
—
ns
189
CAS assertion to RAS assertion (refresh)
tCSR
1.5
× TC 4.0
11.0
—
ns
190
RAS deassertion to CAS assertion (refresh)
tRPC
4.75
× T
C 4.0
43.5
—
ns
191
RD assertion to RAS deassertion
tROH
15.5
× TC 4.0
151.0
—
ns
192
RD assertion to data valid
tGA
14
× TC 5.7
—
134.3
ns
193
RD deassertion to data not valid5
tGZ
0.0
—
ns
194
WR assertion to data active
0.75
× TC – 1.5
6.0
—
ns
195
WR deassertion to data high impedance
0.25
× TC
—2.5
ns
Notes:
1.
The number of wait states for an out-of-page access is specified in the DRAM Control Register.
2.
The refresh period is specified in the DRAM Control Register.
3.
Use the expression to compute the maximum or minimum value listed (or both if the expression includes
±) .
4.
Either tRCH or tRRH must be satisfied for read cycles.
5.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
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