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參數(shù)資料
| 型號： | DSP56301AG80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/124頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 80MHZ GP 208-LQFP |
| 產(chǎn)品變化通告： | DSP56301 Discontinuation 12/Nov/2009 |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | DSP563xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時鐘速率： | 80MHz |
| 非易失內(nèi)存： | ROM（9 kB） |
| 芯片上RAM： | 24kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-LQFP |
| 供應(yīng)商設(shè)備封裝： | 208-LQFP |
| 包裝： | 托盤 |
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DSP56301 Technical Data, Rev. 10
4-4
Freescale Semiconductor
Design Considerations
Equation 5:
Where:
ItypF2
=
current at F2
ItypF1
=
current at F1
F2
=
high frequency (any specified operating frequency)
F1
=
low frequency (any specified operating frequency lower than F2)
Note:
F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The
degree of difference between F1 and F2 determines the amount of precision with which the current rating
can be determined for an application.
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no
test that replicates these exact numbers. These observations were measured on a limited number of parts and were
not verified over the entire temperature and voltage ranges.
4.4.1
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT
for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in
Figure 2-2, External Clock Timing, on page -5 for input frequencies greater than 15 MHz and the MF
≤ 4, this
skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF
< 10 and input frequencies greater than 10 MHz, this skew is between
1.4 ns and +3.2 ns.
4.4.2
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and
CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on
CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz
and MF
≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input
frequencies greater than 10 MHz, this jitter is less than
±2 ns.
4.4.3
Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10)
this jitter is smaller than 0.5 per cent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 per cent and
approximately 2 per cent. For large MF (MF > 500), the frequency jitter is 2–3 per cent.
4.5 Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow
(that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is
fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase
and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.
I MIPS
I MHz
I
typF2
I
typF1
–
() F2 F1
–
()
==
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| DSP56301AG80B1 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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