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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 26/154頁(yè) |
| 文件大小： | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
26
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
4.12 Clock Synthesis
Figure 6. Clock Source Block Diagram
powerc
RING
OSCILLATOR
M
U
X
÷ 2
÷ N
PHASE
DETECTOR
CHARGE
PUMP
VCO
VCO CLOCK
f
VCO
LOOP
FILTER
÷ M
LF[3:0]
Mbits[4:0]
Nbits[2:0]
PLL/SYNTHESIZER
CKI INPUT CLOCK
LOCK
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
f
CKI
f
SLOW CLOCK
SLOWCKI
pllc
PLLEN
INTERNAL
PROCESSOR
CLOCK
f
INTERNAL CLOCK
PLLSEL
f
CKI
5-4520 (F)
The DSP1627 provides an on-chip, programmable
clock synthesizer. Figure 6 is the clock source diagram.
The 1X CKI input clock, the output of the synthesizer, or
a slow internal ring oscillator can be used as the source
for the internal DSP clock. The clock synthesizer is
based on a phase-locked loop (PLL), and the terms
clock synthesizer and PLL are used interchangeably.
On powerup, CKI is used as the clock source for the
DSP. This clock is used to generate the internal proces-
sor clocks and CKO, where f
CKI
= f
CKO
. Setting the ap-
propriate bits in the pllc control register (described in
Table 32) will enable the clock synthesizer to become
the clock source. The powerc register, which is dis-
cussed in Section 4.13, can override the selection to
stop clocks or force the use of the slow clock for low-
power operation.
PLL Control Signals
The input to the PLL comes from one of the three mask-
programmable clock options: CMOS, crystal, or small-
signal. The PLL cannot operate without an external in-
put clock.
To use the PLL, the PLL must first be allowed to stabi-
lize and lock to the programmed frequency. After the
PLL has locked, the LOCK flag is set and the lock detect
circuitry is disabled. The synthesizer can then be used
as the clock source. Setting the PLLSEL bit in the pllc
register will switch sources from f
CKI
to f
VCO
/2 without
glitching. It is important to note that the setting of the pllc
register must be maintained. Otherwise, the PLL will
seek the new set point. Every time the pllc register is
written, the LOCK flag is reset.
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