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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 22/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
22
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
4.8 Parallel Host Interface (PHIF)
The DSP1627 has an 8-bit parallel host interface for rap-
id transfer of data with external devices. This parallel port
is passive (data strobes provided by an external device)
and supports either Motorola or Intel microcontroller pro-
tocols. The PHIF also provides for 8-bit or 16-bit data
transfers. As a flexible host interface, it requires little or
no glue logic to interface to other devices (e.g., microcon-
trollers, microprocessors, or another DSP).
The data path of the PHIF consists of a 16-bit input buff-
er,
pdx0
(in), and a 16-bit output buffer,
pdx0
(out). Two
output pins, parallel input buffer full (PIBF) and parallel
output buffer empty (POBE), indicate the state of the
buffers. In addition, there are two registers used to con-
trol and monitor the PHIF's operation: the parallel host in-
terface control register (
phifc
, see Table 28), and the
PHIF status register (PSTAT, see Table 8). The PSTAT
register, which reflects the state of the PIBF and POBE
flags, can only be read by an external device when the
PSTAT input pin is asserted. The
phifc
register defines
the programmable options for this port.
The function of the pins, PIDS and PODS, is programma-
ble to support both the Inteland Motorolaprotocols. The
pin, PCSN, is an input that, when low, enables PIDS and
PODS (or PRWN and PDS, depending on the protocol
used). While PCSN is high, the DSP1627 ignores any ac-
tivity on PIDS and/or PODS. If a DSP1627 is intended to
be continuously accessed through the PHIF port, PCSN
should be grounded. If PCSN is low and their respective
bits in the
inc
register are set, the assertion of PIDS and
PODS by an external device causes the DSP1627 de-
vice to recognize an interrupt.
Programmability
The parallel host interface can be programmed for 8-bit
or 16-bit data transfers using bit 0, PMODE, of the
phifc
register. Setting PMODE selects 16-bit transfer mode.
An input pin controlled by the host, PBSEL, determines
an access of either the high or low bytes. The assertion
level of the PBSEL input pin is configurable in software
using bit 3 of the
phifc
register, PBSELF. Table 7 sum-
marizes the port's functionality as controlled by the
PSTAT and PBSEL pins and the PBSELF and PMODE
fields.
For 16-bit transfers, if PBSELF is zero, the PIBF and
POBE flags are set after the high byte is transferred. If
PBSELF is one, the flags are set after the low byte is
transferred. In 8-bit mode, only the low byte is accessed,
and every completion of an input or output access sets
PIBF or POBE.
Bit 1 of the
phifc
register, PSTROBE, configures the port
to operate either with an Intelprotocol where only the
chip select (PCSN) and either of the data strobes (PIDS
or PODS) are needed to make an access, or with a Mo-
torolaprotocol where the chip select (PCSN), a data
strobe (PDS), and a read/write strobe (PRWN) are need-
ed. PIDS and PODS are negative assertion data strobes
while the assertion level of PDS is programmable
through bit 2, PSTRB, of the
phifc
register.
Finally, the assertion level of the output pins, PIBF and
POBE, is controlled through bit 4, PFLAG. When PFLAG
is set low, PIBF and POBE output pins have positive as-
sertion levels. By setting bit 5, PFLAGSEL, the logical
OR of PIBF and POBE flags (positive assertion) is seen
at the output pin PIBF. By setting bit 7 in
phifc
, PSOBEF,
the polarity of the POBE flag in the status register,
PSTAT, can be changed. PSOBEF has no effect on the
POBE pin.
Pin Multiplexing
Please refer to Pin Multiplexing in Section 4.1 for a de-
scription of BIO, PHIF, VEC[3:0], and SIO2 pins.
Table 7. PHIF Function (8-bit and 16-bit Modes)
PMODE Field
0 (8-bit)
0
0
0
1 (16-bit)
1
1
1
PSTAT Pin
0
0
1
1
0
0
1
1
PBSEL Pin
0
1
0
1
0
1
0
1
PBSELF Field = 0
pdx0 low byte
reserved
PSTAT
reserved
pdx0 low byte
pdx0 high byte
PSTAT
reserved
PBSELF Field = 1
reserved
pdx0 low byte
reserved
PSTAT
pdx0 high byte
pdx0 low byte
reserved
PSTAT
Table 8. pstat Register as Seen on PB[7:0]
Bit
Field
7
6
5
4
3
2
1
0
RESERVED
PIBF
POBE
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