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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 23/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
23
4 Hardware Architecture
(continued)
4.9 Bit Input/Output Unit (BIO)
The BIO controls the directions of eight bidirectional con-
trol I/O pins, IOBIT[7:0]. If a pin is configured as an output,
it can be individually set, cleared, or toggled. If a pin is
configured as an input, it can be read and/or tested.
The lower half of the
sbit
register (see Table 33) contains
current values (VALUE[7:0]) of the eight bidirectional pins
IOBIT[7:0]. The upper half of the
sbit
register (DI-
REC[7:0]) controls the direction of each of the pins. A log-
ic 1 configures the corresponding pin as an output; a logic
0 configures it as an input. The upper half of the
sbit
reg-
ister is cleared upon reset.
The
cbit
register (see Table 34) contains two 8-bit fields,
MODE/MASK[7:0] and DATA/PAT[7:0]. The values of
DATA/PAT[7:0] are cleared upon reset. The meaning of a
bit in either field depends on whether it has been config-
ured as an input or an output in
sbit
. If a pin has been con-
figured to be an output, the meanings are MODE and
DATA. For an input, the meanings are MASK and PAT
(pattern). Table 9 shows the functionality of the MODE/
MASK and DATA/PAT bits based on the direction select-
ed for the associated IOBIT pin.
Those bits that have been configured as inputs can be in-
dividually tested for 1 or 0. For those inputs that are being
tested, there are four flags produced: allt (all true), allf (all
false), somet (some true), and somef (some false). These
flags can be used for conditional branch or special in-
structions. The state of these flags can be saved and re-
stored by reading and writing bits 0 to 3 of the
alf
register
(see Table 35).
If a BIO pin is switched from being configured as an out-
put to being configured as an input and then back to be-
ing configured as an output, the pin retains the previous
output value.
Pin Multiplexing
Please refer to Pin Multiplexing in Section 4.1 for a
description of BIO, PHIF, VEC[3:0], and SIO2 pins.
4.10 Timer
The interrupt timer is composed of the timerc (control)
register, the timer0 register, the prescaler, and the
counter itself. The timer control register (see Table 31,
timerc Register) sets up the operational state of the timer
and prescaler. The timer0 register is used to hold the
counter reload value (or period register) and to set the
initial value of the counter. The prescaler slows the clock
to the timer by a number of binary divisors to allow for a
wide range of interrupt delay periods.
The counter is a 16-bit down counter that can be loaded
with an arbitrary number from software. It counts down
to 0 at the clock rate provided by the prescaler. Upon
reaching 0 count, a vectored interrupt to program ad-
dress 0x10 is issued to the DSP1627, providing the in-
terrupt is enabled (bit 8 of inc and ins registers). The
counter will then either wait in an inactive state for anoth-
er command from software, or will automatically repeat
the last interrupting period, depending upon the state of
the RELOAD bit in the timerc register.
When RELOAD is 0, the counter counts down from its
initial value to 0, interrupts the DSP1627, and then stops,
remaining inactive until another value is written to the
timer0 register. Writing to the timer0 register causes
both the counter and the period register to be written with
the specified 16-bit number. When RELOAD is 1, the
counter counts down from its initial value to 0, interrupts
the DSP1627, automatically reloads the specified initial
value from the period register into the counter, and re-
peats indefinitely. This provides for either a single timed
interrupt event or a regular interrupt clock of arbitrary pe-
riod.
The timer can be stopped and started by software, and
can be reloaded with a new period at any time. Its count
value, at the time of the read, can also be read by soft-
ware. Due to pipeline stages, stopping and starting the
timer may result in one inaccurate count or prescaled pe-
riod. When the DSP1627 is reset, the bottom 6 bits of the
timerc register and the timer0 register and counter are
initialized to 0. This sets the prescaler to CKO/2*, turns
off the reload feature, disables timer counting, and initial-
izes the timer to its inactive state. The act of resetting the
chip does not cause a timer interrupt. Note that the peri-
od register is not initialized on reset.
The T0EN bit of the timerc register enables the clock to
the timer. When T0EN is a 1, the timer counts down to-
wards 0. When T0EN is a 0, the timer holds its current
count.
*
Frequency of CKO/2 is equivalent to either CKI/2 for the PLL by-
passed or related to CKI by the PLL multiplying factors. See Section
4.12, Clock Synthesis.
Table 9. BIO Operations
DIREC[n]
*
*
0
≤
n
≤
7.
MODE/
MASK[n]
0
0
1
1
0
0
1
1
DATA/
PAT[n]
0
1
0
1
0
1
0
1
Action
1 (Output)
1 (Output)
1 (Output)
1 (Output)
0 (Input)
0 (Input)
0 (Input)
0 (Input)
Clear
Set
No Change
Toggle
No Test
No Test
Test for Zero
Test for One
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