
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
15
4 Hardware Architecture
(continued)
* F3 ALU instructions with immediates require specifying the high half of the accumulators as
a0h
and
a1h
.
Table 3. DSP1600 Core Block Diagram Legend
Symbol
16 x 16 MPY
a0—a1
alf
ALU/SHIFT
auc
c0—c2
cloop
CMP
DAU
i
IDB
inc
ins
j
k
MUX
mwait
p
PC
pi
pr
psw
pt
r0—r3
rb
re
SYS
x
XAAU
XAB
XDB
YAAU
YAB
YDB
ybase
y
Name
16-bit x 16-bit Multiplier.
Accumulators 0 and 1 (16-bit halves specified as
a0
,
a0l
,
a1
, and
a1l
)*.
AWAIT, LOWPR, Flags.
Arithmetic Logic Unit/Shifter.
Arithmetic Unit Control.
Counters 0—2.
Cache Loop Count.
Comparator.
Digital Arithmetic Unit.
Increment Register for the X Address Space.
Internal Data Bus.
Interrupt Control.
Interrupt Status.
Increment Register for the Y Address Space.
Increment Register for the Y Address Space.
Multiplexer.
External Memory Wait-states Register.
Product Register (16-bit halves specified as
p
,
pl
).
Program Counter.
Program Interrupt Return Register.
Program Return Register.
Processor Status Word.
X Address Space Pointer.
Y Address Space Pointers.
Modulo Addressing Register (begin address).
Modulo Addressing Register (end address).
System Cache and Control Section.
Multiplier Input Register.
X Space Address Arithmetic Unit.
X Space Address Bus.
X Space Data Bus.
Y Space Address Arithmetic Unit.
Y Space Address Bus.
Y Space Data Bus.
Direct Addressing Base Register.
DAU Register (16-bit halves specified as
y
,
yl
).