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參數(shù)資料
| 型號： | DS87C550-QNL |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EPROM ADC/PWM HS 68-PLCC |
| 標準包裝： | 18 |
| 系列： | 87C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設備： | 電源故障復位，PWM，WDT |
| 輸入/輸出數(shù)： | 55 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
35 of 49
NOTES FOR DS87C550 DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
These parameters are guaranteed by design.
1. Voltage referenced to digital ground (GND).
2. Active current measured with 33MHz clock source on XTAL1, VCC=RST=5.5V, other pins
disconnected.
3. Idle mode current measured with 33MHz clock source on XTAL1, VCC=5.5V, RST at ground, other
pins disconnected.
4. Stop mode current measured with XTAL1 and RST grounded, VCC=5.5V, all other pins disconnected.
This value is not guaranteed. Users that are sensitive to this specification should contact Dallas
Semiconductor for more information.
5. When addressing external memory.
6. RST=VCC. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when
at a logic high state during I/O mode.
7. During a 0 to 1 transition, a one-shot drives the ports hard for two oscillator clock cycles. This
measurement reflects port in transition mode.
8. Ports 1, 2, 3, 5, 6 source transition current when being pulled down externally. Current reaches its
maximum at approximately 2V.
9. 0.45<VIN<VCC. Not a high-impedance input. This port is a weak address holding latch in Bus Mode.
Peak current occurs near the input transition point of the latch, approximately 2V.
10. 0.45< VIN <VCC. RST=VCC. This condition mimics operation of pins in I/O mode.
11. This is the current required from an external circuit to hold a logic low level on an I/O pin while the
corresponding port latch is set to 1. This is only the current required to hold the low level; transitions
from 1 to 0 on an I/O pin will also have to overcome the transition current.
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