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參數(shù)資料
| 型號： | DS87C550-QNL |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EPROM ADC/PWM HS 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | 87C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，PWM，WDT |
| 輸入/輸出數(shù)： | 55 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
28 of 49
SETR REGISTER FUNCTIONALITY
SETR.7
TGFF1
This bit toggles if CMPH2:CMPL2 and Timer 2 match and CMTE1 is 1
SETR.6
TGFF0
This bit toggles if CMPH2:CMPL2 and Timer 2 match and CMTE0 is 1
SETR.5
CMS5
If 1 then P4.5 is set on a match between CMPH0:CMPL0 and Timer 2
SETR.4
CMS4
If 1 then P4.4 is set on a match between CMPH0:CMPL0 and Timer 2
SETR.3
CMS3
If 1 then P4.3 is set on a match between CMPH0:CMPL0 and Timer 2
SETR.2
CMS2
If 1 then P4.2 is set on a match between CMPH0:CMPL0 and Timer 2
SETR.1
CMS1
If 1 then P4.1 is set on a match between CMPH0:CMPL0 and Timer 2
SETR.0
CMS0
If 1 then P4.0 is set on a match between CMPH0:CMPL0 and Timer 2
RSTR REGISTER FUNCTIONALITY
RSTR.7
CMTE1
If 1 then P4.7 toggles on a match between CMPH2:CMPL2 and Timer 2
RSTR.6
CMTE0
If 1 then P4.6 toggles on a match between CMPH2:CMPL2 and Timer 2
RSTR.5
CMR5
If 1 then P4.5 is reset on a match between CMPH1:CMPL1 and Timer 2
RSTR.4
CMR4
If 1 then P4.4 is reset on a match between CMPH1:CMPL1 and Timer 2
RSTR.3
CMR3
If 1 then P4.3 is reset on a match between CMPH1:CMPL1 and Timer 2
RSTR.2
CMR2
If 1 then P4.2 is reset on a match between CMPH1:CMPL1 and Timer 2
RSTR.1
CMR1
If 1 then P4.1 is reset on a match between CMPH1:CMPL1 and Timer 2
RSTR.0
CMR0
If 1 then P4.0 is reset on a match between CMPH1:CMPL1 and Timer 2
WATCHDOG TIMER
The free-running watchdog timer, if enabled, will set a flag and cause a reset if not restarted by software
within the user selectable timeout period.
A typical application is to allow the flag to cause a reset. When the watchdog times out, it sets the
Watchdog Timer Reset Flag (WTRF=WDCON.2), which generates a reset if enabled by the Enable
Watchdog Timer Reset (EWT=WDCON.1) bit. In this way if the code execution goes awry and software
does not reset the watchdog as scheduled, the processor is put in a known good state: reset.
In a typical initialization, software selects the desired timeout period using the WD1:0 and the system
clock control bits. Then, it resets the timer and enables the processor reset function. After enabling the
processor reset function, software must then reset the timer before its timeout period or hardware will
reset the CPU. A Timed Access circuit protects both the EWT and the Watchdog Reset control (RWT =
WDCON.0) bits. This prevents errant software from accidentally clearing the watchdog.
The watchdog timer is controlled by the Clock Control (CKCON) and the Watchdog Control (WDCON)
SFRs. CKCON.7 and CKCON.6 are WD1 and WD0 respectively, and they select the watchdog timeout
period. Of course, the 4X/ 2X (PMR.3) and CD1:0 (PMR.7:6) system clock control bits also affect the
timeout period. Selection of timeout is shown in Table 8.
WATCHDOG TIMEOUT VALUES Table 8
INTERRUPT TIMEOUT (CLOCKS)
RESET TIME-CLOCKS
4X/ 2X
CD1:0
WD1:0=00
WD1:0=01
WD1:0=10
WD1:0=11
WD1:0=00
WD1:0=01
WD1:0=10
WD1:0=11
1
00
215
218
221
224
215+512
218+512
221+512
224+512
0
00
216
219
222
225
216+512
219+512
222+512
225+512
x
01
217
220
223
226
217+512
220+512
223+512
226+512
x
10
217
220
223
226
217+512
220+512
223+512
226+512
x
11
225
228
231
234
225+512
228+512
231+512
234+512
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