參數(shù)資料
型號(hào): DS83C530-QCL
廠商: DALLAS SEMICONDUCTOR
元件分類: 微控制器/微處理器
英文描述: EPROM/ROM Microcontrollers with Real-Time Clock
中文描述: 8-BIT, UVPROM, 33 MHz, MICROCONTROLLER, CQCC52
封裝: WINDOWED, CERQUAD-52
文件頁數(shù): 33/46頁
文件大?。?/td> 749K
代理商: DS83C530-QCL
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
33 of 46
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 4.5V to 5.5V, T
A
= -40°C to +85°C.)
PARAMETER
Input Leakage Port 0,
EA
, Pins, I/O Mode
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
I
L
I
L
-10
+10
A
13
Input Leakage Port 0, Bus Mode
-300
+300
A
14
RST Pulldown Resistance
R
RST
50
200
k
Note 1:
Storage temperature is defined as the temperature of the device when V
CC
= 0V and V
BAT
= 0V. In this state, the contents of
SRAM are not battery backed and are undefined.
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
All voltages are referenced to ground.
Active current measured with 33MHz clock source on XTAL1, V
CC
= RST = 5.5V, other pins disconnected.
Idle mode current measured with 33MHz clock source on XTAL1, V
CC
= 5.5V, RST at ground, other pins disconnected.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Stop mode current measured with XTAL1 and RST grounded, V
CC
= 5.5V, all other pins disconnected.
Note 7:
Note 8:
V
CC
= 0V, V
BAT
= 3.3V. 32.768kHz crystal with 12.5pF load capacitance between RTCX1 and RTCX2 pins. RTCE bit set to 1.
RST = V
CC
. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when at a logic high state during
I/O mode.
During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition
mode.
When addressing external memory. This specification only applies to the first clock cycle following the transition.
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is
set to 1. This is only the current required to
hold
the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the
transition current.
Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V.
0.45 < V
IN
< V
CC
. RST = V
CC
. This condition mimics operation of pins in I/O mode.
0.45 < V
IN
< V
CC
. Not a high-impedance input. This port is a weak address holding latch in Bus Mode. Peak current occurs near
the input transition point of the latch, approximately 2V.
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
TYPICAL I
CC
vs. FREQUENCY
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