參數(shù)資料
型號(hào): DS83C530-QCL
廠商: DALLAS SEMICONDUCTOR
元件分類: 微控制器/微處理器
英文描述: EPROM/ROM Microcontrollers with Real-Time Clock
中文描述: 8-BIT, UVPROM, 33 MHz, MICROCONTROLLER, CQCC52
封裝: WINDOWED, CERQUAD-52
文件頁(yè)數(shù): 37/46頁(yè)
文件大?。?/td> 749K
代理商: DS83C530-QCL
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
37 of 46
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following is an explanation of the
symbols.
t Time
A Address
C Clock
D Input data
H Logic level high
L Logic level low
POWER-CYCLE TIMING CHARACTERISTICS
I
P
Q
R
V
Instruction
PSEN
Output data
RD
signal
Valid
W
X
WR
signal
No longer a valid logic
level
Tri-State
Z
PARAMETER
SYMBOL
t
CSU
t
POR
MIN
TYP
1.8
MAX
65,536
UNITS
ms
t
CLCL
NOTES
1
2
Cycle Startup Time
Power-On Reset Delay
Note 1:
Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by
Fox.
Reset delay is a synchronous counter of crystal oscillations after crystal startup. At 33MHz, this time is 1.99ms.
Note 2:
EPROM PROGRAMMING AND VERIFICATION
(V
CC
= 4.5V to 5.5V, T
A
= +21°C to +27°C.)
PARAMETER
Programming Voltage
Programming Supply Current
Oscillator Frequency
SYMBOL
V
PP
I
PP
1/t
CLCL
t
AVGL
MIN
12.5
4
48t
CLCL
TYP
MAX
13.0
50
6
UNITS
V
mA
MHz
NOTES
1
Address Setup to
PROG
Low
Address Hold after
PROG
t
GHAX
48t
CLCL
Data Setup to
PROG
Low
t
DVGL
48t
CLCL
Data Hold after
PROG
Enable High to V
PP
t
GHDX
48t
CLCL
t
EHSH
t
SHGL
48t
CLCL
10
V
PP
Setup to
PROG
Low
s
V
PP
Hold after
PROG
t
GHSL
10
s
PROG
Width
Address to Data Valid
Enable Low to Data Valid
Data Float after Enable
t
GLGH
90
110
s
t
AVQV
t
ELQV
t
EHQZ
t
GHGL
48t
CLCL
48t
CLCL
48t
CLCL
0
10
PROG
High to
PROG
Low
s
Note 1:
All voltages are referenced to ground.
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