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參數(shù)資料
| 型號： | DS8007A-EAG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 31/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 應(yīng)用： | 智能卡 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.7 V ~ 6 V |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | 90-8007A+TAG |
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DS8007A
Multiprotocol Dual Smart Card Interface
______________________________________________________________________________________
37
Last Character to Transmit
The ISO UART implements a special control input that
allows an automatic switch from transmit mode
(UCR1.T/R = 1) to receive mode (UCR1.T/R = 0) upon
successful character transmission. The last character
to transmit (UCR1.LCT) bit must be set to 1 by host
software prior to writing the last character for transmis-
sion to UTR. Upon successful transmission of the char-
acter, the UCR1.T/R bit and the LCT bit are cleared by
hardware. When the LCT bit is used, the TBE/RBF bit is
not set at the end of the transmission.
Receive Mode
The ISO UART receive mode is in effect if the associat-
ed UCR1.T/R bit is 0. When the ISO UART is changed
to receive mode, the MSR.FE bit is set to 1 to indicate
that the receive FIFO is empty. When at least one
unread receive character exists in the FIFO, the FE bit
is cleared. When the FIFO, with depth defined by
FL2–FL0, is full, the TBE/RBF bit is set to 1 to indicate
that the receive buffer is full. Once a character is read
from a full FIFO, the RBF/TBE bit is cleared to indicate
that the FIFO is no longer full. The controller ready
(CRED) bit should be polled to assess data readiness
when reading from register URR at high frequencies.
Parity Check
The T = 1 protocol selection checks receive parity. For
T = 1, the parity error count bits (PEC2–PEC0) have no
function and the USR.PE bit are set on the first parity
error.
The T = 0 protocol selection also checks receive parity,
but allows setting of the USR.PE parity error bit to be
based upon detection of 1–8 parity errors. The
PEC2–PEC0 bits define the number of consecutive par-
ity errors that should be detected before setting
USR.PE.
The ISO UART implements a special control input that
allows testing for inverse parity. If the UCR1.FIP bit is
configured to 0 during receive mode, the ISO UART
tests for correct parity on each received character. If
UCR1.FIP is configured to 1, inverse parity is expected.
This control can be useful in testing that the ICC prop-
erly detects error signals generated by the DS8007A
and retransmits requested characters.
LCT BIT WRITTEN TO 1 BY
SOFTWARE, THEN LOAD UTR.
LAST CHARACTER TO TRANSMIT
TBE REMAINS 0, LCT AND
T/R BITS ARE BOTH CLEARED
TO 0 BY HARDWARE.
P
LAST CHARACTER
I/O
TBE/RBF BIT
LCT BIT
T/R BIT
P
Figure 15. Last Character to Transmit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS8007-ENG | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Multiprotocol Dual Smart Card Interface |
| DS8007-ENG+ | 功能描述:接口 - 專用 Multiprotocol Dual Smart Card Interface RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| DS8007-KIT | 功能描述:界面開發(fā)工具 DS8007 Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| DS8008-07 | 制造商:RICHTEK 制造商全稱:Richtek Technology Corporation 功能描述:2.5V to 5.5V Input Range |
| DS800SL-3 | 功能描述:線性和開關(guān)式電源 12V output 760W Gold w/ Reverse Air RoHS:否 制造商:TDK-Lambda 產(chǎn)品:Switching Supplies 開放式框架/封閉式:Enclosed 輸出功率額定值:800 W 輸入電壓:85 VAC to 265 VAC 輸出端數(shù)量:1 輸出電壓（通道 1）:20 V 輸出電流（通道 1）:40 A 商用/醫(yī)用: 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:Rack 長度: 寬度: 高度: |
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