參數(shù)資料
型號: DS8007A-EAG+T
廠商: Maxim Integrated Products
文件頁數(shù): 27/41頁
文件大?。?/td> 0K
描述: IC INTERFACE SMART CARD 48-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
應(yīng)用: 智能卡
接口: 并聯(lián)
電源電壓: 2.7 V ~ 6 V
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
其它名稱: 90-8007A+TAG
DS8007A
Multiprotocol Dual Smart Card Interface
______________________________________________________________________________________
33
Standard Clock Frequencies
and Baud Rates
The DS8007A supports I/O communication and CLKx
frequency generation compliant to the following stan-
dards: ISO 7816, EMV2000, and GSM11-11. Each of
these standards has an allowable CLKx frequency
range and a defined relationship between CLKx fre-
quency and ETU (baud rate) generation that is support-
ed initially and after negotiation.
For ISO 7816, the relationship between ETU (baud rate)
timing and CLKx frequency is as follows:
ETU = (F / D) x (1 / fCLKx)
The minimum CLKx frequency is fixed at 1MHz. The
default maximum CLKx frequency is 5MHz, however,
the maximum CLKx frequency can be increased
according to the Fi parameter given by the card during
ATR. The ISO 7816-1997(3) specification recommends
in Section 4.3.4 that CLKx frequency switches be
made a) immediately after ATR or b) immediately after
a successful PPS exchange. The transmission parame-
ters F and D are respectively the clock-rate conversion
and baud-rate adjustment factors. The notations Fd
and Dd are used to represent the ‘d’efault values for
these parameters, which are Fd = 372 and Dd = 1.
The notation Fi and Di are used to represent the values
‘i’ndicated by the card within the TA(1) character of
ATR. If TA(1) is not present, then Fi, Di are set to the
default Fd, Dd values. The notation Fn and Dn repre-
sent values ‘n’egotiated during a successful PPS
exchange, which should be in the range Fd-Fi and Dd-
Di, respectively. During ATR, the default Fd, Dd values
shall apply. If the card comes up in negotiable mode
(i.e., TA(2) is absent from the ATR), then the Fd, Dd
CLOCK
PRESCALER
PDR
/31: PSC = 0
/32: PSC = 1
PD7:PD0 =
00h TO FFh
CLOCK
PRESCALER
GATE
PDR
/31: PSC = 0
/32: PSC = 1
PD7:PD0 =
00h TO FFh
CLR
(ALIGNED
ETU GENERATOR)
UCR2x.PSC
SOFTWARE
MODE
TO3, TO2,
TO1
10.5 ETU
TO 15 ETU
10.25 ETU
ETU
EN
TOC COUNTERS
CLK
EN
FRACTIONAL ETU
COUNTERS
CLK
EN
FRAME-ERROR-
DETECTED COUNTER
CLK
0.5 ETU
0.25 ETU
CLR
UCR2x.CKU
fCLK
0
1
0
2 x fCLK
RSTx
START BIT
Figure 11. ETU Generation
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