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參數(shù)資料
| 型號(hào)： | DS4830EVKIT# |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT OPTICAL MICROCONTROLLER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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DS4830
Optical Microcontroller
8
Maxim Integrated
SPI DIGITAL InTERFACE SPECIFICATIOn (continued)
(VDD = 2.97V to 3.63V, TA = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
ELECTRICAL CHARACTERISTICS: JTAG InTERFACE
(VDD = 2.97V to 3.63V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 5)
note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
specified as negative.
note 2: Maximum current assuming 100% CPU duty cycle.
note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
note 4: Using internal reference.
note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
note 6: Guaranteed by design.
note 7: ADC conversions are delayed up to 1.6Fs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
note 8: Temperature readings average 64 times.
note 9: Programming time does not include overhead associated with the utility ROM interface.
note 10: fSCL must meet the minimum clock low time plus the rise/fall times.
note 11: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH:MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
note 12: CB—Total capacitance of one bus line in pF.
note 13: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
PARAMETER
SYMBOL
COnDITIOnS
MIn
TYP
MAx
UnITS
SSPIDO Output Valid After
SSPICK Shift Edge Transition
tSOV
2tSPI_RF
ns
SSPICS Inactive
tSSH
tSSPICK +
tSPI_RF
ns
SSPICK Inactive to SSPICS
Rising
tSD
tSPI_RF
ns
SSPIDO Output Disabled After
SSPICS Edge Rise
tSLH
2tSSPICK
+
2tSPI_RF
ns
PARAMETER
SYMBOL
COnDITIOnS
MIn
TYP
MAx
UnITS
JTAG Logic Reference
VREF
VDD/2
V
TCK High Time
tTH
0.5
F
s
TCK Low Time
tTL
0.5
F
s
TCK Low to TDO Output
tTLQ
0.125
F
s
TMS, TDI Input Setup to TCK High
tDVTH
0.25
F
s
TMS, TDI Input Hold After TCK
High
tTHDX
0.25
F
s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS4830EVKIT# | 功能描述:開發(fā)板和工具包 - 其他處理器 DS4830 Eval Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| DS4830RD# | 功能描述:開發(fā)板和工具包 - 其他處理器 REFERENCE DESIGN FOR DS4830/DS3923 RoHS:否 制造商:Maxim Integrated 產(chǎn)品: 工具用于評(píng)估: 核心: 接口類型: 工作電源電壓: |
| DS4830T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Optical Microcontroller 16-Bit MAXQ20 Low-Power Microcontroller |
| DS4830T+ | 功能描述:16位微控制器 - MCU Control Calibration & Opt Trans Mtr RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| DS4830T+T | 功能描述:16位微控制器 - MCU Control Calibration & Opt Trans Mtr RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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