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參數(shù)資料
| 型號： | DS3134 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 189/203頁 |
| 文件大?。?/td> | 777K |
| 代理商： | DS3134 |
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DS3134
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SECTION 7: FIFO
7.1 GENERAL DESCRIPTION & EXAMPLE
Chateau contains one 16k byte FIFO for the receive path and another 16k byte FIFO for the transmit path.
Both of these FIFOs are organized into Blocks. A Block is defined as four dwords (i.e. 16 bytes). Hence,
each FIFO is made up of 1024 Blocks. See the FIFO example in Figure 7.1A.
The FIFO contains a state machine that is constantly polling the 16 ports to determine if any data is ready
for transfer to/from the FIFO from/to the HDLC engines. The 16 ports are priority decoded with Port 0
getting the highest priority and Port 15 getting the lowest priority. Hence, all of the enabled HDLC
channels on the lower numbered ports are serviced before the higher numbered ports. As long as the
maximum throughput rate of 104 Mbps is not exceeded, the DS3134 has been designed to insure that
there is enough bandwidth in this transfer to prevent any loss of data in between the HDLC Engines and
the FIFO.
The FIFO also controls which HDLC channel the DMA should service to read data out of the FIFO on the
receive side and to write data into the FIFO on the transmit side. Which channel gets the highest priority
from the FIFO is configurable via some control bits in the Master Configuration (MC) register (see
Section 4.2). There are two control bits for the receive side (RFPC0 and RFPC1) and two control bits for
the transmit side (TFPC0 and TFPC1) that will determine the priority algorithm as shown in Table 7.1A.
When a HDLC channel is priority decoded the lower the number of the HDLC channel, the higher the
priority. Hence HDLC channel number 1 always has the highest priority in the priority decoded scheme.
FIFO Priority Algorithm Select Table 7.1A
Option
HDLC Channels that are
Priority Decoded
HDLC Channels that are
Serviced Round Robin
1
none
1 to 256
2
1 to 2
3 to 256
3
1 to 16
17 to 256
4
1 to 64
65 to 256
To maintain maximum flexibility for channel reconfiguration, each Block within the FIFO can be
assigned to any of the 256 HDLC channels. In addition, Blocks are link-listed together to form a chain
whereby each Block points to the next Block in the chain. The minimum size of the link-listed chain is 4
Blocks (64 bytes) and the maximum is the full size of the FIFO which is 1024 Blocks.
To assign a set of Blocks to a particular HDLC channel, the Host must configure the Starting Block
Pointer and the Block Pointer RAM. The Starting Block Pointer assigns a particular HDLC channel to a
set of link-listed Blocks by pointing to one of the Blocks within the chain (it does not matter which Block
in the chain is pointed to). The Block Pointer RAM must be configured for each Block that is being used
within the FIFO. The Block Pointer RAM indicates the next Block in the link-listed chain.
Figure 7.1A shows an example of how to configure the Starting Block Pointer and the Block Pointer
RAM. In this example, only three HDLC channels are being used (channels 2, 6, and 16). The device
knows that channel 2 has been assigned to the eight link-listed Blocks of 112, 118, 119, 120, 121, 122,
125, and 126 because a Block Pointer of 125 has been programmed into the channel 2 position of the
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