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參數(shù)資料
| 型號(hào)： | DS3134 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類(lèi)： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 18/203頁(yè) |
| 文件大小： | 777K |
| 代理商： | DS3134 |
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DS3134
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Status Bits / Interrupts
On writes to the Done Queue by the DMA, the DMA will set the Status Bit for Receive DMA Done
Queue Write (RDQW) in the Status Register for DMA (SDMA). The Host can configure the DMA to
either set this status bit on each write to the Done Queue or only after multiple (from 2 to 128) writes.
The Host controls this by setting the RDQT0 to RDQT2 bits in the Receive DMA Queues Control
(RDMAQ) register. See the description of the RDMAQ register at the end of Section 8.1.4 for more
details. The DMA also checks the Receive Done Queue Host Read Pointer to make sure that an overflow
does not occur. If this does occur, then the DMA will set the Status Bit for Receive DMA Done Queue
Write Error (RDQWE) in the Status Register for DMA (SDMA) and it will not write to the Done Queue
nor will it increment the Write Pointer. In such a scenario, packets may be lost and unrecoverable. Each
of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 4 for more details.
Buffer Write Threshold Setting
In the DMA Configuration RAM (see Section 8.1.5), there is a Host controlled field called Threshold
(bits RDT0 to RDT2) that informs the DMA on when it should write to the Done Queue. The Host has
the option to have the DMA place information in the Done Queue after a programmable number (from 1
to 7) data buffers have been filled or wait until the completed packet data has been written. The DMA
will always write to the Done Queue when it has finished receiving a packet even if the threshold has not
been met.
Done Queue Burst Writing
The DMA has the ability to write to the Done Queue in bursts. This allows for a more efficient use of the
PCI Bus. The DMA can hand off descriptors to the Done Queue in-groups rather than one at a time,
freeing up the PCI Bus for more time critical functions.
Internal to the device there is a FIFO that can store up to 8 Done Queue Descriptors (8 dwords since each
descriptor occupies one dword). The Host must configure the FIFO for proper operation via the Receive
DMA Queues Control (RDMAQ) register (see below).
When enabled via the Receive Done Queue FIFO Enable (RDQFE) bit, the Done Queue FIFO will not
write to the Done Queue until it reaches the High Water Mark. When the Done Queue FIFO reaches the
High Water Mark (which is six descriptors), it will attempt to empty the Done Queue FIFO by burst
writing to the Done Queue. Before it writes to the Done Queue, it checks (by examining the Receive
Done Queue Host Read Pointer) to make sure that the Done Queue has enough room to empty the Done
Queue FIFO. If the Done Queue does not have enough room, then it will only burst write enough
descriptors to keep from overflowing the Done Queue. If the FIFO detects that there is no room for any
descriptors to be written, then it will set the Status Bit for Receive DMA Done Queue Write Error
(RDQWE) in the Status Register for DMA (SDMA) and it will not write to the Done Queue nor will it
increment the Write Pointer. In such a scenario, packets may be lost and unrecoverable. If the Done
Queue FIFO can write descriptors to the Done Queue, then it will burst write them, increment the write
pointer, and set the Status Bit for Receive DMA Done Queue Write (RDQW) in the Status Register for
DMA (SDMA). See Section 4 for more details on Status bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
| DS5000FP-12 | 8-BIT, 12 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS-313PIN | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類(lèi)型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
| DS31400DK | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 DS31400 Dev Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| DS31400GN | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Not Available From Mouser RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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