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| 型號(hào)： | DS3134 |
| 廠(chǎng)商： | DALLAS SEMICONDUCTOR |
| 元件分類(lèi)： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 165/203頁(yè) |
| 文件大小： | 777K |
| 代理商： | DS3134 |
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DS3134
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Bit 8 / Receive 56 kbps (R56). If the Port is running a channelized application, this bit determines
whether the LSB of each DS0 should be processed or not. If this bit is set, then the LSB of each DS0
channel will not be routed to the HDLC controller (or the BERT if it has been enabled via the RBERT
bit). This bit does not affect the operation of the V.54 detector (it always searches on all 8 bits in the
DS0).
0 = 64 kbps (use all 8 bits in the DS0)
1 = 56 kbps (use only the first seven bits received in the DS0)
Bit 10 / Channelized Local LoopBack Enable (CLLB). Enabling this loopback forces the transmit data
to replace the receive data. This bit must be set for each and every DS0 channel that is to be looped back.
In order for the loopback to become active, the DS0 channel must be enabled (RCHEN = 1) and the DS0
channel must be set into the 64 kbps mode (R56 = 0).
0 = loopback disabled
1 = loopback enabled
Bit 12 / Receive V.54 Enable (RV54E). If this bit is cleared, this DS0 channel will not be examined to
see if the V.54 loop pattern is present. If set, the DS0 will be examined for the V.54 loop pattern. When
searching for the V.54 pattern within a DS0 channel, all 8 bits of the DS0 channel are examined
regardless of how the DS0 channel is configured (i.e. 64k or 56k).
0 = do not examine this DS0 channel for the V.54 loop pattern
1 = examine this DS0 channel for the V.54 loop pattern
Bit 14 / Route Data Into BERT (RBERT). Setting this bit will route the DS0 data into the BERT
function. If the DS0 channel has been configured for 56 kbps operation (R56 = 1), then the LSB of each
DS0 channel is not routed to the BERT block. In order for the data to make it to the BERT block, the
Host must also configure the BERT for the proper port via the Master Control register (see Section 4).
0 = do not route data to BERT
1 = route data to BERT
Bit 15 / Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a
channelized application. In a channelized application, although a DS0 channel is deactivated, the channel
can still be set up to route data to the V.54 detector and/or the BERT block. In addition, although a DS0
channel is active, the loopback function (CLLB = 1) overrides this activation and will route transmit data
back to the HDLC controller instead of the data coming in via the RD pin. In an unchannelized mode
(RUEN = 1), only the RCHEN bit in R[n]CFG0 needs to be configured.
0 = deactivated DS0 channel
1 = active DS0 channel
Register Name:
T[n]CFG[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0
Register Description: Transmit Layer 1 Configuration Register
Register Address:
Indirect Access via CP[n]RD
76
5432
10
TCH#(8): Transmit HDLC Channel Number
15
14
13
12
11
10
9
8
TCHEN
TBERT
n/a
CNLB
n/a
TFAO
T56
Note: Bits that are underlined are read only, all other bits are read-write.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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