
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 
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7.2 Instruction Register 
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the 
TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI and JTDO. 
While in the shift-IR state, a rising edge on TCLK with JTMS LOW will shift the data one stage towards the serial 
output at JTDO. A rising edge on TCLK in the exit1-IR state or the exit2-IR state with JTMS HIGH will move the 
controller to the update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift 
register to the instruction parallel output. Instructions supported by the DS26303 and its respective operational 
binary codes are shown in 
Table 7-1
. 
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture  
INSTRUCTION 
EXTEST 
HIGHZ 
CLAMP 
SAMPLE/PRELOAD 
IDCODE 
BYPASS 
SELECTED REGISTER 
Boundary Scan 
Bypass 
Bypass 
Boundary Scan 
Device Identification 
Bypass 
INSTRUCTION CODES 
000 
010 
011 
100 
110 
111 
EXTEST 
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction 
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output 
pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will 
sample all digital inputs into the boundary scan register. 
HIGHZ 
All digital outputs of the device will be placed in a HIGHZ state. The BYPASS register will be connected between 
JTDI and JTDO. 
CLAMP 
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass 
register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. 
SAMPLE/PRELOAD 
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the 
device can be sampled at the boundary scan register without interfering with the normal operation of the device by 
using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan 
register via JTDI using the Shift-DR state. 
IDCODE 
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is 
selected. The device identification code will be loaded into the identification register on the rising edge of TCLK 
following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. 
During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The ID code 
will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number 
of continuation bytes followed by 16 bits for the device and 4 bits for the version 
Table 7-2
. 
Table 7-3
 lists the 
device ID code for the DS26303. 
BYPASS 
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal 
operation.