
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 
12 of 97 
PIN 
NAME 
eLQFP 
PBGA 
TYPE 
FUNCTION 
DIGITAL Tx/Rx 
TPOS1/TDATA1 
TPOS2/TDATA2 
TPOS3/TDATA3 
TPOS4/TDATA4 
TPOS5/TDATA5 
TPOS6/TDATA6 
TPOS7/TDATA7 
TPOS8/TDATA8 
TNEG1 
37 
30 
80 
73 
108 
101 
8 
1 
38 
N2 
L2 
L13 
N13 
B13 
D13 
D2 
B2 
N3 
I 
Transmit Positive-Data Input for Channel 1 to 8/Transmit Data 
Input for Channel 1 to 8 
TPOS[1:8]: 
When the DS26303 is configured in dual-rail mode, the 
data input to TPOSn is output as a positive pulse on the line (TIP 
and RING). 
TDATA[1:8]:
When the device is configured in single-rail mode, 
NRZ data is input to TDATAn. The data is encoded HDB3/B8ZS or 
AMI before being output to the line. 
TNEG2 
31 
L3 
TNEG3 
79 
L12 
TNEG4 
72 
N12 
TNEG5 
109 
B12 
TNEG6 
102 
D12 
TNEG7 
7 
D3 
TNEG8 
144 
B3 
I 
Transmit Negative Data for Channel 1 to 8. 
When the DS26303 
is configured in dual-rail mode, the data input to TNEGn is output 
as a negative mark on the line as follows: 
TPOSn     TNEGn      Output Pulse 
0               0                 Space 
0               1                 Negative Mark 
1               0                 Positive Mark 
1               1                 Space 
When TNEGn is pulled High for more than 16 consecutive TCLK 
clock cycles, single-rail I/O is selected. 
TCLK1 
36 
N1 
TCLK2 
29 
L1 
TCLK3 
81 
L14 
TCLK4 
74 
N14 
TCLK5 
107 
B14 
TCLK6 
100 
D14 
TCLK7 
9 
D1 
TCLK8 
2 
B1 
I 
Transmit Clock for Channel 1 to 8.
 The transmit clock must be 
1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock 
used to sample the data TPOS/TNEG or TDAT on the falling edge. 
The expected TCLK can be inverted. 
If TCLKn is high for 16 or more MCLKs, then transmit all-ones 
(TAO) signals to the line side of the corresponding transmit 
channel. When TCLKn starts clocking again, normal operation will 
begin again for the corresponding transmit channel. 
If TCLKn is low for 64 or more MCLKs, the corresponding transmit 
channel on the line side powers down and must be put into high 
impedance. When TCLKn starts clocking again the corresponding 
transmit channel powers up and comes out of high impedance. 
Receive Positive-Data Output for Channel 1 to 8/Receive Data 
Output for Channel 1 to 8 
RPOS1/RDATA1 
RPOS2/RDATA2 
RPOS3/RDATA3 
RPOS4/RDATA4 
RPOS5/RDATA5 
RPOS6/RDATA6 
RPOS7/RDATA7 
RPOS8/RDATA8 
40 
33 
77 
70 
111 
104 
5 
142 
P2 
M2 
M13 
P13 
A13 
C13 
C2 
A2 
O,  
tri-state 
RPOS[1:8]:
In dual-rail mode, the NRZ data output indicates a 
positive pulse on RTIP/RRING. If a given receiver is in power-
down mode, the associated RPOS pin is high impedance. 
RDATA[1:8]
: In single-rail mode, NRZ data is output to the pin. 
Note: During an RLOS condition, the RPOS/RDATA outputs 
remain active. 
Receive Negative-Data Output for Channel 1 to 8/Code 
Violation for Channel 1 to 8 
RNEG1/CV1 
41 
P3 
RNEG2/CV2 
34 
M3 
RNEG3/CV3 
76 
M12 
RNEG4/CV4 
69 
P12 
RNEG5/CV5 
112 
A12 
O,  
tri-state 
RNEG[1:8]:
In dual-rail mode, the NRZ data output indicates a 
negative pulse on RTIP/RRING. If a given receiver is in power-
down mode, the associated RNEG pin is high impedance. 
CV[1:8]:
In single-rail mode, bipolar violation, code violation, and 
excessive zeros are reported by driving CVn high for one clock