
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 
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6.4.5 Bipolar Violation and Excessive Zero Detector 
The DS26303 detects code violations, BPV, and excessive zero errors. The reporting of the errors is done through 
the pin RNEGn/CVn. 
Excessive zeros are detected if eight consecutive 0s are detected with B8ZS enabled and four consecutive 0s are 
detected with HDB3 enabled. Excessive zero detection is selectable when single-rail mode and HDB3/B8ZS 
encoding/decoding is selected. 
The bits in 
EZDE
 and 
CVDEB
 registers determine the combinations that are reported. 
Table 6-9
 outlines the 
functionality: 
Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting 
CONDITIONS 
CVn PIN REPORTS 
BPV + code violation 
BPV + code violation + excessive zero 
BPV 
BPV + excessive zero 
EZDE is reset, CVDEB is reset 
EZDE is set, CVDEB is reset 
EZDE is reset, CVDEB is set 
EZDE is set, CVDEB is set 
6.4.6 LIU Receiver Front End 
It is recommended that the receiver be configured as per 
Table 6-4
 and 
Figure 6-4
. Internal or external mode for 
the receiver front end can be selected by register 
GC.RIMPMS
. When this bit is set to external mode the user is 
required to supply two 15  resistors as shown in 
Figure 6-4
. The internal adjust resistors A75, A100, and A110 will 
still be set in external mode if 75 , 100 , or 110  impedance is selected during template selection. However, the 
internal 30  resistor will be disconnected. If the user would like all the adjust resistors to be disconnected or any 
internal impedance matching, then the user should set the 
TS.RIMPOFF
 bit for each LIU or the RIMPOFF pin when 
in hardware mode. 
6.5 Hitless-Protection Switching (HPS) 
Many current redundancy protection implementations use mechanical relays to switch between primary and 
backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The 
switching event likely causes frame-synchronization loss in any equipment downstream, affecting the quality of 
service. The same is also true for tri-stating mechanisms that use software or inactive clocks for the triggering of 
HPS. 
The DS26303 LIU includes fast tri-statable outputs for TTIP and TRING and fast turn-off impedance matching for 
the RTIP and RRING within less than one bit cycle. The control logic is shown in 
Figure 6-5
. In software mode, the 
user can set the RHPMC bit, which allows the OE pin to control both the transmitter outputs and the receive 
impedance matching. This is a very useful function in that control can be done through a hardware pin, allowing a 
quick switch to the backup system for both the receiver and the transmitter. 
Figure 6-6
 shows a typical HPS 
application in software mode where the OE is used for control. In hardware mode, the receiver can have 
impedance matching turned off quickly by using the RIMPOFF pin, and the transmitter output can be turned off 
quickly by using the OE pin.