- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1915 > DS26303LN-75+A3 (Maxim Integrated Products)IC LIU E1/T1/J1 3.3V 144-ELQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | DS26303LN-75+A3 |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 7/101頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP 裸露焊盤(pán) |
| 包裝： | 托盤(pán) |
| 其它名稱： | 90-26303+7N3 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
13 of 101
NAME
PIN
TYPE
FUNCTION
RNEG1/CV1
41
RNEG2/CV2
34
RNEG3/CV3
76
RNEG4/CV4
69
RNEG5/CV5
112
RNEG6/CV6
105
RNEG7/CV7
4
RNEG8/CV8
141
O,
tri-state
Receive Negative-Data Output for Channel 1 to 8/Code
Violation for Channel 1 to 8
RNEG[1:8]:
In dual-rail mode, this output indicates a negative
pulse on RTIPn/RRINGn. If a given receiver is in power-down
mode, the corresponding RNEGn pin is high impedance.
CV[1:8]:
In single-rail mode, bipolar violation, code violation, and
excessive zeros are reported by driving CVn high for one clock
cycle. If HDB3 or B8ZS encoding is not selected, this pin indicates
only BPVs.
Note: During an RLOS condition, the RNEGn/CVn output remains
active.
RCLK1
39
RCLK2
32
RCLK3
78
RCLK4
71
RCLK5
110
RCLK6
103
RCLK7
6
RCLK8
143
O,
tri-state
Receive Clock for Channel 1 to 8.
The receive data
RPOSn/RNEGn or RDATn is clocked out on the rising edge of
RCLKn. RCLKn can be inverted. If a given receiver is in power-
down mode, RCLKn is high impedance.
MCLK
10
I
Master Clock.
This is an independent free-running clock that can
be a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz
±50ppm for T1 mode. The clock selection is available by MC bits
MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be
internally adapted to 1.544MHz and a multiple of 1.544MHz can
be internally adapted to 2.048MHz. In hardware mode, internal
adaptation is not available so the user must provide 2.048MHz
±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode.
RLOS1/TECLK
42
O
Loss-of-Signal Output/T1-E1 Clock
RLOS1:
This output goes high when there are no transitions on
the receiveline over a specified interval. The output goes low when
there is sufficient ones density on the receiveline. The RLOS
assertion and desertion criteria are described in the Functional
Description
section. The RLOS outputs can be configured to
comply with T1.231, ITU-T G.775, or ETS 300 233. In hardware
mode, ETS 300 233 “RLOS Criteria” is not available.
TECLK:
When enabled (MC.TECLKE is set), this output becomes
a T1- or E1-programmable clock output. For T1 or E1 frequency
selection, see the CCR register. This option is not available in
hardware mode.
RLOS2
35
RLOS3
75
RLOS4
68
RLOS5
113
RLOS6
106
RLOS7
3
RLOS8
140
O
Loss-of-Signal Output
RLOS[2:8]: RLOS2:
This output goes high when there are no
transitions on the receiveline over a specified interval. The output
goes low when there is sufficient ones density on the receiveline.
The RLOS assertion and desertion criteria are described in the
Functional Description
(Section 6). The RLOS outputs can be
configured to comply with T1.231, ITU-T G.775, or ETS 300 233.
In hardware mode, ETS 300 233 “RLOS Criteria” is not available.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS26324GNA2+ | IC INTERFACE LINE 16CH 256-CSBGA |
| DS26334GN+ | IC INTERFACE LINE 16CH 256-CSBGA |
| DS26401N+ | IC OCTAL FRAMER T1/E1/J1 256-BGA |
| DS26504LNB2+ | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS26514G+ | IC TXRX T1/E1/J1 4PORT 256-CSBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303LN-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26-32.768-STD-020 | 制造商:Micro Crystal Switzerland 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。