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參數(shù)資料
| 型號： | DS26303LN-75+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 68/101頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 13 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP 裸露焊盤 |
| 供應商設備封裝： | 144-LQFP 裸露焊盤 |
| 包裝： | 托盤 |
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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After configuring these bits, the pattern must be loaded into the BERT. This is accomplished through a 0-to-1
Monitoring the BERT requires reading the BSR register that contains the BEC bit and the OOS bit. The BEC bit is 1
when the bit-error counter is 1 or more. The OOS is 1 when the receive pattern generator is not synchronized to
the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64-bit window. The receive
BERT bit-count register (RBCR) and the receive BERT bit-error count register (RBECR) are updated upon the
reception of a performance-monitor update signal (e.g., BCR.LPMU). This signal updates the registers with the
values of the counters since the last update and resets the counters.
6.9.2
BERT Interrupt Handling
There are four BERT events that can potentially trigger an interrupt. A performance monitoring update, a bit error, a
non-zero bit error count, or an Out Of Synchronization (OOS). The interrupt functions as follows:
When a status bit (BSR:PMS, BEC, or OOS) changes on an interruptible event, the corresponding interrupt
status bit (BSRL.PMSL BEL, BECL, or OOSL) is set. The
INTB pin will go low if the event is enabled through
the corresponding interrupt-enable bit (BSRIE.PMSIE BEIE, BECIE, or OOSIE).
When an interrupt occurs, the host processor must read the interrupt status register (BSRL) to determine the
source of the interrupt. If the interrupt status registers are set for clear-on-read (GISC.CWE reset), the read
also clears the Interrupt Status register which clears the output
INTB pin. If the interrupt status registers are set
for (GISC.CWE set), a 1 must be written to the interrupt status bit (BSRL.PMSL BEL, BECL, or OOSL) in order
to clear it which clears the output
INTB pin.
Subsequently, the host processor can read the status register (BSR) to check the real-time status of the event.
6.9.3
Receive Pattern Detection
The receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial x
n + xy + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to 1 if the
next 14 bits are all 0s. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is forced to
1 if bits 1 through 31 are all 0s. Depending on the type of pattern programmed, pattern detection performs either
PRBS synchronization or repetitive pattern synchronization.
6.9.3.1
Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
re-synchronization is initiated. Automatic pattern resynchronization can be disabled.
See Figure 6-12 for the PRBS synchronization diagram.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303LN-75+ | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| DS26303LN-75+A3 | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| DS26303LN-75A3 | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| DS26303LN-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
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