- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97868 > DS2423X (DALLAS SEMICONDUCTOR) SPECIALTY MEMORY CIRCUIT, UUC PDF資料下載
參數(shù)資料
| 型號： | DS2423X |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Memory IC:Other |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, UUC |
| 封裝： | CHIP SCALE PKG |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 579K |
| 代理商： | DS2423X |
DS2422/DS2423
19 of 25
1-WIRE SIGNALING
The DS242X requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. All these signals except presence pulse are initiated by the bus master. The DS242X can
communicate at two different speeds, regular speed and Overdrive Speed. If not explicitly set into the
Overdrive mode, the DS242X will communicate at regular speed. While in Overdrive Mode the fast
timing applies to all waveforms.
The initialization sequence required to begin any communication with the DS242X is shown in Figure 10.
A reset pulse followed by a presence pulse indicates the DS242X is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a reset pulse
(tRSTL, minimum 480 s at regular speed, 48 s at Overdrive Speed). The bus master then releases the line
and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After
detecting the rising edge on the data pin, the DS242X waits (tPDH, 15-60 s at regular speed, 2-6 s at
Overdrive speed) and then transmits the presence pulse (tPDL, 60-240 s at regular speed, 8-24 s at
Overdrive Speed).
A Reset Pulse of 480 s or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS242X is in Overdrive Mode and the Reset Pulse is no longer than 80 s the device will remain in
Overdrive Mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS242X to the master
by triggering a delay circuit in the DS242X. During write time slots, the delay circuit determines when
the DS242X will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS242X will hold the data line low overriding the 1 generated by the
master. If the data bit is a “1“, the device will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2423 | 4K X 1 STANDARD SRAM, PDSO6 |
| DS2422 | 1K X 1 STANDARD SRAM, PDSO6 |
| DS2430AP | 256 X 1 1-WIRE SERIAL EEPROM, PDSO6 |
| DS2430A | 32 X 8 1-WIRE SERIAL EEPROM, PBCY3 |
| DS2430AX | 32 X 8 1-WIRE SERIAL EEPROM, UUC2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS243 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DS2430 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430A | 功能描述:電可擦除可編程只讀存儲器 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| DS2430A R | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430A T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。