- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97868 > DS2422X (DALLAS SEMICONDUCTOR) SPECIALTY MEMORY CIRCUIT, UUC PDF資料下載
參數(shù)資料
| 型號(hào)： | DS2422X |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Memory IC:Other |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, UUC |
| 文件頁(yè)數(shù)： | 12/23頁(yè) |
| 文件大小： | 146K |
| 代理商： | DS2422X |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
DS2422/DS2423
021998 2/23
The battery–backed memory offers a simple solution to
storing and retrieving information pertaining to the
equipment where the DS242X is installed and its fre-
quency of use. The scratchpad is an additional page
that acts as a buffer when writing to memory. Data is first
written to the scratchpad where it may be read back for
verification.
A copy scratchpad command will then
transfer the data to memory. This process insures data
integrity when modifying the memory. A 64–bit registra-
tion number is factory lasered into each DS242X to pro-
vide a guaranteed unique identity which allows for abso-
lute traceability and acts as node address if multiple
DS242X are connected in parallel to form a local net-
work. Data is transferred serially via the 1–Wire proto-
col which requires only a single data lead and a ground
return.
The DS242X 1–Wire RAM With Counters can store
encrypted data. The unique registration number and
the page write cycle counter(s) prevent unauthorized
manipulation of data stored in a page with a write cycle
counter associated.
OVERVIEW
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS242X. The DS242X has four main data components:
1) 64–bit lasered ROM, 2) 256–bit scratchpad, 3)
1024–bit (DS2422) or 4096–bit (DS2423) SRAM, and 4)
three (DS2422) or four (DS2423) 32–bit read–only
counters. The hierarchical structure of the 1–Wire pro-
tocol is shown in Figure 2. Each of these counters is
associated with one of the 256–bit memory pages. The
three counters of the DS2422 are associated with pages
1 to 3; the four counters of the DS2423 are associated
with pages 12 to 15. The contents of the counter is read
together with the memory data using a special com-
mand. The bus master must first provide one of the six
ROM Function Commands, 1) Read ROM, 2) Match
ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive–Skip
ROM or 6) Overdrive–Match ROM. Upon completion of
an overdrive ROM command byte executed at standard
speed, the device will enter Overdive mode where all
subsequent communication occurs at a higher speed.
The protocol required for these ROM function com-
mands is described in Figure 9. After a ROM function
command is successfully executed, the memory func-
tions become accessible and the master may provide
any one of the five memory function commands. The
protocol for these memory function commands is
described in Figure 7. All data is read and written least
significant bit first.
PARASITE POWER
The block diagram (Figure 1) shows the parasite–pow-
ered circuitry. This circuitry “steals” power whenever
the I/O input is high. I/O will provide sufficient power as
long as the specified timing and voltage requirements
are met. The advantages of parasite power are two–
fold: 1) by parasiting off this input, lithium is conserved
and 2) if the battery is exhausted for any reason, the
ROM may still be read normally.
64–BIT LASERED ROM
Each DS242X contains a unique ROM code that is 64
bits long. The first eight bits are a 1–Wire family code.
The next 48 bits are a unique serial number. The last
eight bits are a CRC of the first 56 bits (See Figure 3).
The 1–Wire CRC is generated using a polynomial gen-
erator consisting of a shift register and XOR gates as
shown in Figure 4. The polynomial is X8 + X5 + X4 + 1.
Additional information about the Dallas 1–Wire Cyclic
Redundancy Check is available in the Book of DS19xx
iButtonTM Standards.
The shift register bits are initialized to zero. Then start-
ing with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, then the serial number is entered.
After the 48th bit of the serial number has been entered,
the shift register contains the CRC value. Shifting in the
eight bits of CRC should return the shift register to all
zeros.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2423P/T&R | SPECIALTY MEMORY CIRCUIT, PDSO6 |
| DS2423P | SPECIALTY MEMORY CIRCUIT, PDSO6 |
| DS2423X | SPECIALTY MEMORY CIRCUIT, UUC |
| DS2423 | 4K X 1 STANDARD SRAM, PDSO6 |
| DS2422 | 1K X 1 STANDARD SRAM, PDSO6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2423 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:4kbit 1-Wire RAM with Counter |
| DS2423D/T&R | 制造商:Maxim Integrated Products 功能描述:IC SRAM 4KBIT 6FLIPCHIP |
| DS2423D/T&R | 功能描述:IC SRAM 4KBIT 6FCHIP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF) |
| DS2423MRAB0 | 制造商:Thomas & Betts 功能描述:300A,NLT,3P4W,MG,423,3P480V |
| DS2423P | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。