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參數(shù)資料
| 型號(hào)： | DS2415X |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 0K |
| 描述： | IC TIME CHIP 1-WIRE CSP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 10,000 |
| 類型： | 二進(jìn)制計(jì)數(shù)器 |
| 特點(diǎn)： | 唯一 ID |
| 時(shí)間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | 1 線 串行 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-XBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 6-覆晶（2.82x2.54） |
| 包裝： | 帶卷 (TR) |
DS2415
14 of 14
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C, VPUP = 2.5V to 6.0V, VBAT = 2.5V to 5.5V)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Time Slot
tSLOT
60
120
ms
Write 1 Low Time
tLOW1
115
ms
14
Write 0 Low Time
tLOW0
60
120
ms
Read Low Time
tLOWR
115
ms
14
Read Data Valid
tRDV
15
ms
13
Release Time
tRELEASE
015
45
ms
Read Data Setup
tSU
1
ms
6
Recovery Time
tREC
1
ms
Reset Time High
tRSTH
480
ms
5
Reset Time Low
tRSTL
480
960
ms
8
Presence Detect High
tPDH
15
60
ms
Presence Detect Low
tPDL
60
240
ms
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VPUP = external pullup voltage.
4. Input load is to ground.
5. An additional reset or communication sequence cannot begin until the reset high time has expired.
6. Read data setup time refers to the time the bus master must pull the I/O line low to read a bit. Data is
guaranteed to be valid within 1
ms of this falling edge.
7. Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
8. The reset low time (tRSTL) should be restricted to a maximum of 960
ms, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
9. When VBAT ramps up, the oscillator is always off.
10. At VBAT = 3V
± 10%
11. At VBAT = 5V
± 10%
12. VIH1 has to be VBAT -0.3V or higher.
13. The optimal sampling point for the master is as close as possible to the end time of the 15s tRDV
period without exceeding tRDV. For the case of a Read-One Time Slot, this maximizes the amount of
time for the pull-up resistor to recover to a high level. For a Read-Zero Time Slot, it ensures that a
read will occur before the fastest 1-Wire device(s) release the line.
14. The duration of the low pulse sent by the master should be a minimum of 1s with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
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