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DS21FF42/DS21FT42
5 of 115
17.
ELASTIC STORES OPERATION ................................................................................... 62
17.1 RECEIVE SIDE ............................................................................................................ 63
17.2 TRANSMIT SIDE.......................................................................................................... 63
17.3 MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE............................. 63
18.
HDLC CONTROLLER..................................................................................................... 64
18.1 HDLC FOR DS0S ........................................................................................................... 64
19.
FDL/FS EXTRACTION AND INSERTION....................................................................... 65
19.1 HDLC AND BOC CONTROLLER FOR THE FDL ........................................................ 65
19.1.1 General Overview................................................................................................... 65
19.1.2 Status Register for the HDLC ................................................................................. 66
19.1.3 HDLC/BOC Register Description............................................................................ 68
19.2 LEGACY FDL SUPPORT............................................................................................. 76
19.2.1 Overview.................................................................................................................76
19.2.2 Receive Section ..................................................................................................... 76
19.2.3 Transmit Section .................................................................................................... 77
19.3 D4/SLC–96 OPERATION............................................................................................. 78
20.
PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION ...................... 78
21.
TRANSMIT TRANSPARENCY ....................................................................................... 81
22.
INTERLEAVED PCM BUS OPERATION........................................................................ 82
23.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................... 84
23.1 DESCRIPTION ................................................................................................................. 84
23.2 TAP CONTROLLER STATE MACHINE................................................................................. 85
23.3 INSTRUCTION REGISTER AND INSTRUCTIONS ..................................................................... 88
23.4 TEST REGISTERS ............................................................................................................ 90
24.
TIMING DIAGRAMS........................................................................................................ 95
25.
OPERATING PARAMETERS ....................................................................................... 103
26.
MCM PACKAGE DIMENSIONS ................................................................................... 114