參數(shù)資料
型號: DS21FF42N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 100/115頁
文件大小: 534K
代理商: DS21FF42N
DS21FF42/DS21FT42
85 of 115
The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0).
The JTAG
feature is disabled when the DS21Q42 is configured for emulation of the DS21Q41B (FMS = 1). FMS is
tied to ground for the DS21FF42/DS21FT42.Details on Boundary Scan Architecture and the Test Access
Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See
the pin descriptions for details.
BOUNDARY SCAN ARCHITECTURE Figure 23-1
23.2 TAP CONTROLLER STATE MACHINE
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.
Please see Figure 23.2 for details on each of the states described below.
Tap Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK.
Test-Logic-Reset
Upon power up of the DS21Q42, the TAP Controller will be in the Test-Logic-Reset state.
The
Instruction register will contain the IDCODE instruction. All system logic of the DS21Q42 will operate
normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
Test registers will remain idle.
Select-DR-Scan
+V
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
JTDI
JTMS
JTCLK
JTRST
JTDO
+V
Test Access Port
Controller
MUX
10K
Select
Output Enable
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