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參數(shù)資料
| 型號： | DS2181A |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX CEPT PRIMARY RATE 40-DIP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 10 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | CEPT |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應商設備封裝： | 40-PDIP |
| 包裝： | 管件 |
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DS2181A
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REGISTER SUMMARY Table 5
REGISTE
R
ADDRE
SS
T/R
1
DESCRIPTION/FUNCTION
RIMR
0000
R
Receive Interrupt Mask Register. Allows masking of alarm
generated interrupts.
RSR
0001
R
2
Receive Status Register. Reports all receive alarm conditions.
BVCR
0010
R
Bipolar Violation Count Register. 8-bit presettable counter
which records individual bipolar violations.
CECR
0011
R
CRC4 Error Count Register. 8-bit presettable counter which
records individual errors.
FECR
0100
R
Frame Error Count Register. 8-bit presettable counter which
logs individual errors in the received frame alignment signal.
RCR
0101
R
Receive Control Register. Establishes receive side operating
characteristics.
CCR
0110
T/R
Common Control Register. Establishes additional operating
characteristics for transmit and receive sides.
TCR
0111
T
Transmit Control Register. Establishes transmit side operation
characteristics.
TIR1
TIR2
TIR3
TIR4
1000
1001
1010
1011
T
Transmit Idle Registers. Designates which outgoing timeslots are
to be substituted with idle code.
TINR
1100
T
Transmit International and National Register. When enabled via
the TCR, contents inserted into the outgoing national and/or
international bit positions.
TXR
1101
T
Transmit Extra Register. When enabled via the TCR, contents
inserted into the out going extra bit positions.
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations must be programmed to 0.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a microprocessor/ microcontroller-compatible serial port.
Fourteen on-chip registers allow the user to update operational characteristics and monitor device status
via a host controller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads
and/ or writes by the host. The timing set is identical to that of 8051-type microcontrollers operating in
serial port mode 0. For proper operation of the port and the transmit and receive registers, the user should
provide TCLK and RCLK as well as SCLK.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS2181A+ | 功能描述:網(wǎng)絡控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AN | 功能描述:網(wǎng)絡控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AQ | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AQ/T&R | 制造商:Maxim Integrated Products 功能描述:CEPT TRANCEIVER-PLCC-TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TXRX CEPT PRIMARY RATE 44PLCC |
| DS2181AQ/T&R+ | 制造商:Maxim Integrated Products 功能描述:CEPT TRNSCVR 1TX 1RX 44PLCC - Tape and Reel |
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