參數資料
型號: DS2181A
廠商: Maxim Integrated Products
文件頁數: 14/32頁
文件大?。?/td> 0K
描述: IC TXRX CEPT PRIMARY RATE 40-DIP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 10
類型: 收發(fā)器
驅動器/接收器數: 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應商設備封裝: 40-PDIP
包裝: 管件
DS2181A
21 of 32
RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 19
(MSB)
(LSB)
RRA
RDMA
RSA1
RUA1
FSERR
MFSERR
RLOS
ECS
SYMBOL
POSITION
NAME AND DESCRIPTION
RRA
RIMR.7
Receive Remote Alarm
1 = Interrupt enabled
0 = Interrupt masked
RDMA
RIMR.6
Receive Distant Multiframe Alarm
1 = Interrupt enabled
0 = Interrupt masked
RSA1
RIMR.5
Receive Signaling All 1’s
1 = Interrupt enabled
0 = Interrupt masked
RUA1
RIMR.4
Receive Unframed All 1’s
1 = Interrupt enabled
0 = Interrupt masked
FSERR
RIMR.3
Frame Resync Criteria Met
1 = Interrupt enabled
0 = Interrupt masked
MFSERR
RIMR.2
CAS Multiframe Resync Criteria Met
1 = Interrupt enabled
0 = Interrupt masked
RLOS
RIMR.1
Receive Loss of Sync
1 = Interrupt enabled
0 = Interrupt masked
ECS
RIMR.0
Error Count Saturation
1 = Interrupt enabled
0 = Interrupt masked
ALARM REPORTING AND INTERRUPT SERVICING
Alarm and error conditions are reported at outputs and the RSR. Use of the RSR and error count registers
simplifies system error monitoring. The RSR can be read in one of two ways: a burst read does not
disturb the RSR contents; a direct read will clear all bits set in the RSR unless the alarm condition which
set them is still active. Interrupts are enabled via the RIMR and are generated whenever an alarm or error
condition sets an RSR bit. The host controller must service the transceiver in order to clear an interrupt
condition. Clearing the appropriate RIMR bit will unconditionally clear an interrupt.
BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 20
(MSB)
(LSB)
BVD7
BVD6
BVD5
BVD4
BVD3
BVD2
BVD1
BVD0
SYMBOL
POSITION
NAME AND DESCRIPTION
BVD7
BVCR.7
MSB of bipolar violation count.
BVD0
BVCR.0
LSB of bipolar violation count.
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