1,2 SERIAL PORT (0 °C to 70°C; V DD
參數(shù)資料
型號: DS2181A
廠商: Maxim Integrated Products
文件頁數(shù): 21/32頁
文件大?。?/td> 0K
描述: IC TXRX CEPT PRIMARY RATE 40-DIP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 10
類型: 收發(fā)器
驅動器/接收器數(shù): 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應商設備封裝: 40-PDIP
包裝: 管件
DS2181A
28 of 32
AC ELECTRICAL CHARACTERISTICS
1,2 SERIAL PORT
(0
°C to 70°C; V
DD = 5.0V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
SDI to SCLK Setup
tDC
50
ns
SCLK to SDI Hold
tCDH
50
ns
SCLK Low Time
tCL
244
ns
SCLK High Time
tCH
244
ns
SCLK Rise and Fall Time
tR, tF
100
ns
CS
to SCLK Setup
tCC
50
ns
SCLK to CS Hold
tCCH
50
ns
CS
Inactive Time
tCWH
2.5
ns
SLK to SDO Valid
tCDV
200
ns
CS
to SDO High Z
tCDZ
75
ns
NOTES:
1. Measured at VIH =2.0 V; VIL =.8 V and 10 ns maximum rise and fall time.
2. Output load capacitance = 100 pF.
AC ELECTRICAL CHARACTERISTICS
1,2 – TRANSMIT
(0
°C to 70°C; V
DD = 5.0V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
TCLK Period
tP
488
ns
TCLK Pulse Width
tWL, tWH
244
ns
TCLK Raise & Fall Time
tW, tR
20
ns
TSER, TSD, TIND and TXD
Setup to TCLK Falling
tSTD
50
ns
TSER, TSD, TIND and TXD
Hold to TCLK Falling
tHTD
50
ns
TFSYNC, TMSYNC Setup to
TCLK Falling
tSTS
75
ns
TFSYNC, TMSYNC Hold to
TCLK Falling
tHTS
50
ns
Propagation Delay TCLK to
TCHCLK, TSTS, TMO, TAF
tPTS
75
ns
NOTES:
1. Measured at VIH = 2.0V; VIL = .8V and 10 ns maximum rise and fall time.
2. Output load capacitance = 100 pF.
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