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參數(shù)資料
| 型號(hào)： | DS2181A+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX CEPT PRIMARY RATE 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | CEPT |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
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DS2181A
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ADDRESS/COMMAND
An address/command byte write must precede any read or write of the port registers. The first bit written
(LSB) of the address/command byte specifies read or write. The following nibble identifies register
address. The next 2 bits are reserved and must be set to 0 for proper operation. The last bit of the
address/command word enables the burst mode when set; the burst mode allows consecutive reading or
writing of all register data. Data is written to and read from the port LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Data is sampled on the rising edge of SCLK.
Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are
terminated and SDO tri-stated when CS returns to high.
CLOCKS
To access the serial port registers both TCLK and RCLK are required along with the SCLK. The TCLK
and RCLK are used to internally access the transmit and receive registers, respectively. The CCR is
considered a receive register for this purpose.
DATA I/O
Following the eight SCLK cycles that input the address/ command byte, data at SDI is strobed into the
addressed register on the next eight SCLK cycles (register write) or data is presented at SDO on the next
eight SCLK cycles (register read). SDO is tri-stated during writes and may be tied to SDI in applications
where the host processor has bi-directional I/O capability.
BURST MODE
The burst mode allows all on-chip registers to be consecutively read or written by the host processor. This
feature minimizes device initialization time on system power-up or reset. Burst mode is initiated when
ACB.7 is set and the address nibble is 0000. All registers must be read or written during the burst mode.
If CS transitions high before the burst is complete, data validity is not guaranteed.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB)
(LSB)
BM
-
ADD3
ADD2
ADD1
AD0
R/W
SYMBOL
POSITION
NAME AND DESCRIPTION
BM
ACB.7
Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.
-
ACB.6
Reserved, must be 0 for proper operation.
-
ACB.5
Reserved, must be 0 for proper operation.
ADD3
ACB.4
MSB of register address.
ADD2
ACB.3
ADD1
ACB.2
ADD0
ACB.1
LSB of register address.
R/W
ACB.0
Read/Write Select.
0 = write addressed register.
1 = read addressed register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2181A+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AQ/T&R | 制造商:Maxim Integrated Products 功能描述:CEPT TRANCEIVER-PLCC-TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TXRX CEPT PRIMARY RATE 44PLCC |
| DS2181AQ/T&R+ | 制造商:Maxim Integrated Products 功能描述:CEPT TRNSCVR 1TX 1RX 44PLCC - Tape and Reel |
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