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| 型號： | DS2181A+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX CEPT PRIMARY RATE 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | CEPT |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
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DS2181A
10 of 32
RCR: RECEIVE CONTROL REGISTER Figure 6
(MSB)
(LSB)
-
RSM
CMSC
CMRC
FRC
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
-
RCR.7
Reserved; must be 0 for proper operation.
-
RCR.6
Reserved; must be 0 for proper operation.
RSM
RCR.5
Received Signaling Mode
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
CMSC
RCR.4
CAS Multiframe Sync Criteria
0 = Declare sync when fixed sync criteria met.
1 = Declare sync when fixed criteria are met and two additional
consecutive valid multiframe alignment signals are detected.
CMRC
RCR.3
CAS Multiframe Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if two consecutive timeslot
16 words have values of 0 in the first four MSB positions
(0000xxxx).
FRC
RCR.2
Frame Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if bit 2 in timeslot 0 of non-
align frames is received in error on three consecutive occasions.
SYNCE
RCR.1
Sync Enable
If clear, the synchronizer will automatically begin resync if error
criteria are met. If high, no auto resync occurs.
RESYNC
RCR.0
Resync
When toggled low to high, the receive synchronizer will initiate
immediately.
The bit must be cleared, then set again for
subsequent resyncs.
CEPT FRAME STRUCTURE
The CEPT frame is made up of 32 8-bit channels (time-slots) numbered from 0 to 31. The frame
alignment signal in bit positions 2 through 8 of timeslot 0 of every other frame is independent of the
various multiframe modes described below. Outputs TAF and RAF indicate frames which contain the
alignment signal. Timeslot 0 of frames not containing the frame alignment signal is used for alarm and
national data. See the separate DS2181A CEPT Transceiver Application Note for more details.
CAS SIGNALLING
CEPT networks support Channel Associated Signaling (CAS) or Common Channel Signaling (CCS).
These signaling modes are independently selectable for transmit and receive sides.
CAS (selected when TCR.5 = 0 and/or when RCR.5 = 0) is a bit-oriented signaling technique which
utilizes a 16-frame multiframe. The multiframe alignment signal (0-hex), extra and alarm bits occupy
timeslot 16 of frame 0. Timeslot 16 of the remaining 15 frames is reserved for channel signaling data.
Four signaling bits (A, B, C and D) are transmitted once per multiframe as shown in Figure 7. Input
TMSYNC establishes the transmitted CAS multiframe position. Signaling data can be sourced from input
TSD (TCR.6 = 1) or multiplexed into TSER (TCR.6 = 0).
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