A high-low transition on RST clears all internal registers excep" />
參數(shù)資料
型號: DS2181A+
廠商: Maxim Integrated Products
文件頁數(shù): 18/32頁
文件大小: 0K
描述: IC TXRX CEPT PRIMARY RATE 40-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 10
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
DS2181A
25 of 32
RESET
A high-low transition on RST clears all internal registers except the three error counters; a resync is
initiated until RST returns high. RST must be held low on system power-up and when switching to/from
the hardware mode. Following reset, the host processor should update all on-chip registers to establish
desired operating modes.
HARDWARE MODE
An on-chip hardware control mode simplifies preliminary system prototyping and serves applications
which do not require the features of the serial port. Tying SPS low disables the serial port, clears all
internal register locations except those shown below, and redefines pins 14 through 18 as mode control
inputs. The mode control inputs establish device operational characteristics as shown in Table 8. The
hardware mode simplifies device retrofit into existing applications where control interfaces are designed
with discrete logic.
HARDWARE MODE CONTROL Table 8
PIN NUMBER
REGISTER LOCATION
NAME AND DESCRIPTION
14
(16)
TINR.5
TRA - Transmit Remote Alarm
0 = Normal operation
1 = Enable alarm
15
(17)
TXR.2
TDMA - Transmit Distant Multiframe
Alarm
0 = Normal operation
1 = Enable alarm
16
(18)
CCR.5/CCR.4
Data Format
0 = Input and output data AMI coded
1 = Input and output data HDB3 coded
17
(19)
CCR.3/CCR.2
Transmit and Receive CRC4 Multiframe
0 = Disabled
1 = Enabled
18
(20)
TCR.5/RCR.5
Transmit and Receive CAS Multiframe
0 = Enabled
1 = Disabled
NOTE:
1. Pin numbers for PLCC package are listed in parenthesis.
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