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參數(shù)資料
| 型號： | DS2164Q |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Codec |
| 英文描述： | A/MU-LAW, ADPCM CODEC, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 304K |
| 代理商： | DS2164Q |
DS2164Q
12 of 17
TIME SLOT RESTRICTIONS
Under certain conditions, the DS2164Q does contain some restrictions on the output time slots that are
available. These restrictions are covered in detail in a separate application note. No restrictions occur if
the DS2164Q is operated in the hardware mode.
INPUT TO OUTPUT DELAY
With all three compressions algorithms, the total delay, from the time the PCM data sample is captured
by the DS2164Q to the time it is output, is always less than 375
s. The exact delay is determined by the
input and output time slots selected for each channel.
CHANNEL ASSOCIATED SIGNALING
The DS2164Q supports Channel Associated Signaling (CAS) via its ability to automatically change from
the 32 kbps compression algorithm to the 24 kbps algorithm. If the DS2164Q is configured to perform
the 32kbps algorithm, then in both the hardware and software mode, it will sense the frame sync inputs
(FSX and FSY) for a double-wide frame sync pulse. Whenever the DS2164Q receives a double-wide
pulse, it will automatically switch from the 32kbps algorithm to the 24kbps algorithm. Switching to the
24 kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM output
because this bit does not contain any useful speech information.
ON-THE-FLY ALGORITHM SELECTION
In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the
DS2164Q does not need to be reset or stopped to make the change from one algorithm to another. The
DS2164Q reads the Control Register before it starts to process each PCM or ADPCM sample. If the user
wishes to switch algorithms, then the Control Register must be updated via the serial port before the first
input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and
ACPCM outputs will tristate during register updates.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2165QL | A/MU-LAW, ADPCM CODEC, PQCC28 |
| DS2165Q | A/MU-LAW, ADPCM CODEC, PQCC28 |
| DS2165QN | A/MU-LAW, ADPCM CODEC, PQCC28 |
| DS2172T | SPECIALTY TELECOM CIRCUIT, PQFP32 |
| DS2172TN | SPECIALTY TELECOM CIRCUIT, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2164Q/T&R | 制造商:Maxim Integrated Products 功能描述:ADPCM PROCESSOR 28PIN PLCC T&R - Tape and Reel |
| DS2164Q/T&R+ | 制造商:Maxim Integrated Products 功能描述:ADPCM PROCESSOR 28P PLCC T&R LF - Tape and Reel |
| DS2164Q/T&R | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DS2164Q+ | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DS2164Q+T&R | 制造商:Maxim Integrated Products 功能描述:ADPCM PROCESSOR 28PLCC - Tape and Reel |
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