參數(shù)資料
型號: DS2154LD2+
廠商: Maxim Integrated Products
文件頁數(shù): 47/87頁
文件大?。?/td> 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2154
51 of 87
9 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2154 can replace data on a channel-by-channel basis in both the transmit and receive directions.
The transmit direction is from the backplane to the E1 line and is covered in Section 9.1. The receive
direction is from the E1 line to the backplane and is covered in Section 9.2.
9.1 Transmit Side Code Generation
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the DS2154. The first method, which is covered in Section 9.1.1, was
a feature contained in the original DS2153 while the second method, which is covered in Section 9.1.2, is
a new feature of the DS2154.
9.1.1 Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8-bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to 0.
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel
Loopback (PCLB). If the CCR3.5 control bit is set to 1, then the TIRs will determine which channels (if
any) from the backplane should be replaced with the data from the receive side or, in other words, off of
the E1 line. See Figure 1-1. If this mode is enabled, then transmit and receive clocks and frame syncs
must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC. There are no restrictions on which channels can be looped back or on how many channels can
be looped back.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
(Also used for Per-Channel Loopback.)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1 (26)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2 (27)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3 (28
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TIR4 (29)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH32
TIR4.7
Transmit Idle Registers.
0 = do not insert the Idle Code in the TIDR into this channel
CH1
TIR1.0
1 = insert the Idle Code in the TIDR into this channel
Note: If CCR3.5 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be
sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see Figure 1-1).
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