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參數(shù)資料
| 型號(hào)： | DS2153Q-A7+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 58/60頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX E1 1-CHIP 5V 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | E1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 65mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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DS2153Q
7 of 60
PIN
NAME
TYPE
FUNCTION
20
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the
function listed in parentheses ().
21, 22
RTIP,
RRING
—
Receive Tip and Ring. Analog inputs for clock recovery circuitry;
connects to a 1:1 transformer (see Section 13 for details).
23
RVDD
—
Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and
TVDD pins.
24
RVSS
—
Receive Signal Ground. 0V. Should be tied to local ground plane.
25, 26
XTAL1,
XTAL2
—
Crystal Connections. A pullable 8.192MHz crystal must be applied to
these pins. See Section 13 for crystal specifications.
27
INT1
O
Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain output.
28
INT2
O
Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
29
TTIP
—
Transmit Tip. Analog line driver output; connects to a step-up
transformer (see Section 13 for details).
30
TVSS
—
Transmit Signal Ground. 0V. Should be tied to local ground plane.
31
TVDD
—
Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and
RVDD pins.
32
TRING
—
Transmit Ring. Analog line driver outputs; connects to a step-up
transformer (see Section 13 for details).
33
TCHBLK
O
Transmit Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section 14 for
timing details.
34
TLCLK
O
Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK
input. Controlled by TCR2. See Section 14 for timing details.
35
TLINK
I
Transmit Link Data. If enabled, this pin will be sampled on the falling
edge of TCLK to insert the Sa bits. See Section 14 for timing details.
36
TSYNC
I/O
Transmit Sync. A pulse at this pin will establish either frame or
multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q
can be programmed to output either a frame or multiframe pulse at this
pin. See Section 14 for timing details.
37
DVDD
—
Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD
pins.
38
TCLK
I
Transmit Clock. 2.048MHz primary clock.
39
TSER
I
Transmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
40
TCHCLK
O
Transmit Channel Clock. 256kHz clock that pulses high during the
LSB of each channel. Useful for parallel to serial conversion of channel
data. See Section 14 for timing details.
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| DS2156LN+ | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2153QN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| DS2153QN-A5 | 功能描述:IC TXRX E1 1-CHIP 5V IND 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS2153QN-A7 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2153QN-A7/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS2153QN-A7/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER E1/ISDN-PRI/PCM-30 5V 44PLCC - Tape and Reel |
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