參數(shù)資料
型號(hào): DS2153Q-A7+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/60頁(yè)
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 單芯片收發(fā)器
接口: E1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2153Q
19 of 60
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
(MSB)
(LSB)
TESF
TESE
JALT
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
POSITION
NAME AND DESCRIPTION
TESF
RIR.7
Transmit Elastic Store Full. Set when the elastic store fills and
a frame is deleted.
TESE
RIR.6
Transmit Elastic Store Empty. Set when the elastic store
empties and a frame is repeated.
JALT
RIR.5
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
RESF
RIR.4
Elastic Store Full. Set when the elastic store buffer fills and a
frame is deleted.
RESE
RIR.3
Elastic Store Empty. Set when the elastic store buffer empties
and a frame is repeated.
CRCRC
RIR.2
CRC Resync Criteria Met. Set when 915/1000 codewords are
received in error.
FASRC
RIR.1
FAS Resync Criteria Met. Set when three consecutive FAS
words are received in error.
CASRC
RIR.0
CAS Resync Criteria Met. Set when two consecutive CAS MF
alignment words are received in error.
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