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參數(shù)資料
| 型號： | DS2152LN |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁數(shù)： | 61/94頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | DS2152LN |
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DS2152
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11.2 LEGACY FDL SUPPORT
11.2.1 Overview
In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the
circuitry that existed in the previous generation of T1 Single-Chip Transceivers. Section 11.2 covers the
circuitry and operation of this legacy functionality. In new applications, it is recommended that the
HDLC controller and BOC controller described in Section 11.1 be used. On the receive side, it is possible
to have both the new HDLC/BOC controller and the legacy hardware working at the same time.
However, this is not possible on the transmit side since their can be only one source the of the FDL data
internal to the device.
11.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
DS2152 will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2 ms to read this data before it is lost.
If the byte in the RFDL matches either of the bytes
programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT
pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the
FDL or Fs pattern until an important event occurs.
The DS2152 also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2152 will
automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically
remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The
CCR2.0 bit should always be set to a 1 when the DS2152 is extracting the FDL. More on how to use the
DS2152 in FDL applications in this legacy support mode is covered in a separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address=28 Hex)
(MSB)
(LSB)
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RFDL7
RFDL.7
MSB of the Received FDL Code
RFDL0
RFDL.0
LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2152L | DATACOM, FRAMER, PQFP100 |
| DS2153Q | DATACOM, FRAMER, PQCC44 |
| DS2154L | DATACOM, FRAMER, PQFP100 |
| DS21554L | DATACOM, PCM TRANSCEIVER, PQFP100 |
| DS21554LN | DATACOM, PCM TRANSCEIVER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2152LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2153DK | 功能描述:KIT DESIGN TXRX E1 DS2153 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2153Q | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Single-Chip Transceiver |
| DS2153Q-A5 | 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS2153Q-A5/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC |
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