
DS2152
2 of 93
TABLE OF CONTENTS
1.0
INTRODUCTION ..................................................................................... 4
Block Diagram...............................................................................................................................
6
Pin List...........................................................................................................................................
7
Pin Description ..............................................................................................................................
9
Register Map..................................................................................................................................
13
2.0
PARALLEL PORT................................................................................... 17
3.0
CONTROL, ID, AND TEST REGISTERS ................................................ 18
Payload Loopback .........................................................................................................................
23
Framer Loopback...........................................................................................................................
23
Pulse Density Enforcer ..................................................................................................................
25
Local Loopback .............................................................................................................................
27
Power-up Sequence .......................................................................................................................
29
Remote Loopback ..........................................................................................................................
29
4.0
STATUS AND INFORMATION REGISTERS .......................................... 30
5.0
ERROR COUNT REGISTERS ................................................................ 38
Line Code Violation Count Register .............................................................................................
39
Path Code Violation Count Register..............................................................................................
39
Multiframes Out of SYNC Count Register ...................................................................................
40
6.0
DSO MONITORING FUNCTION ............................................................. 41
7.0
SIGNALING OPERATION....................................................................... 44
Processor Based Signaling..........................................................................................................
44
Hardware Based Signaling..........................................................................................................
46
8.0
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......... 47
Transmit Side Code Generation.....................................................................................................
47
Receive Side Code Generation ......................................................................................................
49
9.0
CLOCK BLOCKING REGISTERS .......................................................... 51
10.0 ELASTIC STORES OPERATION............................................................ 52
11.0 FDL/FS EXTRACTION AND INSERTION................................................ 53
HDLC and BOC Controller for the FDL.......................................................................................
53
Legacy FDL Support .....................................................................................................................
63
D4/SLC-96 Operation....................................................................................................................
64
12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION 65
13.0 TRANSMIT TRANSPARENCY................................................................ 68