參數(shù)資料
型號： DS2152LN
英文描述： Enhanced T1 Single-Chip Transceiver
中文描述： 增強型T1單芯片收發(fā)器
文件頁數(shù)： 49/94頁
文件大?。?/td> 1003K
代理商： DS2152LN
DS2152
49 of 93
8.1.1 Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is
used, then the CCR4.0 control bit must be set to 0.
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed-bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel
Loop-Back (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or, in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS
(Address=3C to 3E Hex)
[Also used for Per-Channel Loopback]
(MSB) (LSB)
CH8
CH7
CH6
CH5
CH16
CH15
CH14
CH13
CH24
CH23
CH22
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
CH1
CH9
CH17
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TIR3.7
Transmit Idle Registers.
0=do not insert the Idle Code in the TIDR into this channel
CH1
TIR1.0
1=insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies
that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback;
see Figure 1-1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER
(Address=3F Hex)
(MSB) (LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR.7
MSB of the Idle Code (this bit is transmitted first)
TIDR0
TIDR.0
LSB of the Idle Code (this bit is transmitted last)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2152LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2153DK 功能描述:KIT DESIGN TXRX E1 DS2153 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP
DS2153Q 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Single-Chip Transceiver
DS2153Q-A5 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS2153Q-A5/T&R 制造商:Maxim Integrated Products 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC
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